summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--arch/arc/cpu/arc700/cache.c29
-rw-r--r--arch/arc/include/asm/arcregs.h2
2 files changed, 31 insertions, 0 deletions
diff --git a/arch/arc/cpu/arc700/cache.c b/arch/arc/cpu/arc700/cache.c
index 39d522d22f..fa19a13b7e 100644
--- a/arch/arc/cpu/arc700/cache.c
+++ b/arch/arc/cpu/arc700/cache.c
@@ -14,21 +14,34 @@
#define DC_CTRL_CACHE_DISABLE (1 << 0)
#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
#define DC_CTRL_FLUSH_STATUS (1 << 8)
+#define CACHE_VER_NUM_MASK 0xF
int icache_status(void)
{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+ return 0;
+
return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
IC_CTRL_CACHE_DISABLE;
}
void icache_enable(void)
{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
~IC_CTRL_CACHE_DISABLE);
}
void icache_disable(void)
{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
IC_CTRL_CACHE_DISABLE);
}
@@ -43,24 +56,40 @@ void invalidate_icache_all(void)
int dcache_status(void)
{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ return 0;
+
return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
DC_CTRL_CACHE_DISABLE;
}
void dcache_enable(void)
{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
}
void dcache_disable(void)
{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
DC_CTRL_CACHE_DISABLE);
}
void flush_dcache_all(void)
{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
/* Do flush of entire cache */
write_aux_reg(ARC_AUX_DC_FLSH, 1);
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 5d48d11bab..8ace87fa0f 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -24,6 +24,7 @@
#if (CONFIG_ARC_MMU_VER > 2)
#define ARC_AUX_IC_PTAG 0x1E
#endif
+#define ARC_BCR_IC_BUILD 0x77
/* Timer related auxiliary registers */
#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
@@ -42,6 +43,7 @@
#if (CONFIG_ARC_MMU_VER > 2)
#define ARC_AUX_DC_PTAG 0x5C
#endif
+#define ARC_BCR_DC_BUILD 0x72
#ifndef __ASSEMBLY__
/* Accessors for auxiliary registers */