summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorJason Jin <Jason.jin@freescale.com>2008-09-27 14:40:57 +0800
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-10-07 15:37:08 -0500
commitc0391111c33c22fabeddf8f4ca801ec7645b4f5c (patch)
tree38f34ae2b3cdb04300ee0c5afb08e9317c2e5d05 /include
parentbac6a1d1fa1cd80aa57881fa9c2152b853cd0ed4 (diff)
Fix the incorrect DDR clk freq reporting on 8536DS
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/immap_85xx.h7
-rw-r--r--include/configs/MPC8536DS.h2
2 files changed, 8 insertions, 1 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 559d6ea6ca..50c9ddefd2 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1552,6 +1552,13 @@ typedef struct par_io {
*/
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
+#ifdef CONFIG_MPC8536
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
+#else
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
+#endif
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 2578bef278..0d65b206ba 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -59,7 +59,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
-/* #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /\* ddrclk for MPC85xx *\/ FIXME-8536*/
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
from ICS307 instead of switches */