sunxi: add initial clock setup for sun9i for SPL

1 files changed, 79 insertions, 2 deletions

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index 1e73d7dd6a..b79eceaba2 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -105,8 +105,6 @@ struct sunxi_sysctl_reg {
 	u32 disp_mux_cfg;       /* 0x38 display MUX control */
 };
 
-/* pll4_periph0_cfg */
-#define PLL4_CFG_DEFAULT		0x90002800 /* 960 MHz */
 
 #define CCM_PLL4_CTRL_N_SHIFT		8
 #define CCM_PLL4_CTRL_N_MASK		(0xff << CCM_PLL4_CTRL_N_SHIFT)
@@ -115,6 +113,80 @@ struct sunxi_sysctl_reg {
 #define CCM_PLL4_CTRL_M_SHIFT		18
 #define CCM_PLL4_CTRL_M_MASK		(0x1 << CCM_PLL4_CTRL_M_SHIFT)
 
+/* pllx_cfg bits */
+#define CCM_PLL1_CTRL_N(n)		(((n) & 0xff) << 8)
+#define CCM_PLL1_CTRL_P(n)		(((n) & 0x1) << 16)
+#define CCM_PLL1_CTRL_EN		(1 << 31)
+#define CCM_PLL1_CLOCK_TIME_2		(2 << 24)
+
+#define CCM_PLL2_CTRL_N(n)		(((n) & 0xff) << 8)
+#define CCM_PLL2_CTRL_P(n)		(((n) & 0x1) << 16)
+#define CCM_PLL2_CTRL_EN		(1 << 31)
+#define CCM_PLL2_CLOCK_TIME_2		(2 << 24)
+
+#define CCM_PLL4_CTRL_N(n)		(((n) & 0xff) << 8)
+#define CCM_PLL4_CTRL_EN		(1 << 31)
+
+#define CCM_PLL6_CTRL_N(n)		(((n) & 0xff) << 8)
+#define CCM_PLL6_CTRL_P(p)		(((p) & 0x1) << 16)
+#define CCM_PLL6_CTRL_EN		(1 << 31)
+#define CCM_PLL6_CFG_UPDATE             (1 << 30)
+
+#define CCM_PLL12_CTRL_N(n)		(((n) & 0xff) << 8)
+#define CCM_PLL12_CTRL_EN		(1 << 31)
+
+#define PLL_C0CPUX_STATUS               (1 << 0)
+#define PLL_C1CPUX_STATUS               (1 << 1)
+#define PLL_DDR_STATUS                  (1 << 5)
+#define PLL_PERIPH1_STATUS              (1 << 11)
+
+/* cpu_clk_source bits */
+#define C0_CPUX_CLK_SRC_SHIFT           0
+#define C1_CPUX_CLK_SRC_SHIFT           8
+#define C0_CPUX_CLK_SRC_MASK            (1 << C0_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_MASK            (1 << C1_CPUX_CLK_SRC_SHIFT)
+#define C0_CPUX_CLK_SRC_OSC24M		(0 << C0_CPUX_CLK_SRC_SHIFT)
+#define C0_CPUX_CLK_SRC_PLL1		(1 << C0_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_OSC24M		(0 << C1_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_PLL2		(1 << C1_CPUX_CLK_SRC_SHIFT)
+
+/* c0_cfg */
+#define C0_CFG_AXI0_CLK_DIV_RATIO(n)    (((n - 1) & 0x3) << 0)
+#define C0_CFG_APB0_CLK_DIV_RATIO(n)    (((n - 1) & 0x3) << 8)
+
+/* ahbx_cfg */
+#define AHBx_SRC_CLK_SELECT_SHIFT       24
+#define AHBx_SRC_MASK                   (0b11 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB0_SRC_GTBUS_CLK              (0b00 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB1_SRC_GTBUS_CLK              (0b00 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB2_SRC_OSC24M                 (0b00 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_SRC_PLL_PERIPH0            (0b01 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_SRC_PLL_PERIPH1            (0b10 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_CLK_DIV_RATIO(n)           (((ffs(n) - 1) & 0x3) << 0)
+
+/* apb0_cfg */
+#define APB0_SRC_CLK_SELECT_SHIFT       24
+#define APB0_SRC_MASK                   (0b1 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_SRC_OSC24M                 (0b0 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_SRC_PLL_PERIPH0            (0b1 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_CLK_DIV_RATIO(n)           (((ffs(n) - 1) & 0x3) << 0)
+
+/* gtbus_clk_cfg */
+#define GTBUS_SRC_CLK_SELECT_SHIFT      24
+#define GTBUS_SRC_MASK                  (0b11 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_OSC24M                (0b00 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_PLL_PERIPH0           (0b01 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_PLL_PERIPH1           (0b10 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_CLK_DIV_RATIO(n)          (((n - 1) & 0x3) << 0)
+
+/* cci400_clk_cfg */
+#define CCI400_SRC_CLK_SELECT_SHIFT     24
+#define CCI400_SRC_MASK                 (0b11 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_OSC24M               (0b00 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_PLL_PERIPH0          (0b01 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_PLL_PERIPH1          (0b10 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_CLK_DIV_RATIO(n)         (((n - 1) & 0x3) << 0)
+
 /* sd#_clk_cfg fields */
 #define CCM_MMC_CTRL_M(x)		((x) - 1)
 #define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
@@ -165,6 +237,11 @@ struct sunxi_sysctl_reg {
 #define CCM_GMAC_CTRL_TX_CLK_DELAY(x)	     ((x) << 10)
 
 #ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int clk);
+void clock_set_pll2(unsigned int clk);
+void clock_set_pll4(unsigned int clk);
+void clock_set_pll6(unsigned int clk);
+void clock_set_pll12(unsigned int clk);
 unsigned int clock_get_pll4_periph0(void);
 #endif