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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-11-03 10:05:22 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-11-03 10:05:22 +0100
commita42c87f9d831c4eb36104255766cc7897876867c (patch)
tree90dd6a5dad0e7e290d7df44cff746fb3319b3219
parentd598e0fe739e5a75db74cc144beabd09e3c51433 (diff)
parenta956bdcb3ff759f753e3f0c5e40e58f4c3056e22 (diff)
Merge remote-tracking branch 'u-boot-ti/master'
Diffstat
-rw-r--r--MAINTAINERS8
-rw-r--r--README4
-rw-r--r--arch/arm/cpu/armv7/am33xx/clock.c35
-rw-r--r--arch/arm/cpu/armv7/omap3/board.c28
-rw-r--r--arch/arm/include/asm/setup.h5
-rw-r--r--arch/arm/lib/bootm.c4
-rw-r--r--board/8dtech/eco5pk/Makefile43
-rw-r--r--board/8dtech/eco5pk/eco5pk.c61
-rw-r--r--board/8dtech/eco5pk/eco5pk.h404
-rw-r--r--board/nokia/rx51/Makefile46
-rw-r--r--board/nokia/rx51/lowlevel_init.S209
-rw-r--r--board/nokia/rx51/rx51.c677
-rw-r--r--board/nokia/rx51/rx51.h389
-rw-r--r--board/nokia/rx51/tag_omap.h311
-rw-r--r--board/ti/am335x/board.c24
-rw-r--r--board/ti/am335x/board.h5
-rw-r--r--board/ti/am335x/mux.c80
-rw-r--r--boards.cfg9
-rw-r--r--doc/README.nokia_rx51104
-rw-r--r--drivers/serial/serial_ns16550.c36
-rw-r--r--drivers/video/cfb_console.c328
-rw-r--r--include/configs/am335x_evm.h12
-rw-r--r--include/configs/eco5pk.h81
-rw-r--r--include/configs/nokia_rx51.h452
-rw-r--r--include/twl4030.h98
25 files changed, 3421 insertions, 32 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 5a500c5a24..12fa853cac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -571,6 +571,10 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
edminiv2 ARM926EJS (Orion5x SoC)
+Raphael Assenat <raph@8d.com>
+
+ eco5pk ARM ARMV7 (AM35x SoC)
+
Stefano Babic <sbabic@denx.de>
ea20 davinci
@@ -1015,6 +1019,10 @@ Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
armadillo-800eva R8A7740 (RMOBILE SoC)
+Pali Rohár <pali.rohar@gmail.com>
+
+ nokia_rx51 ARM ARMV7 (OMAP34xx SoC)
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
diff --git a/README b/README
index 69da2b86ba..2572add573 100644
--- a/README
+++ b/README
@@ -661,6 +661,10 @@ The following options need to be configured:
additional board info beside
the logo
+ When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
+ a limited number of ANSI escape sequences (cursor control,
+ erase functions and limited graphics rendition control).
+
When CONFIG_CFB_CONSOLE is defined, video console is
default i/o. Serial console can be forced with
environment 'console=serial'.
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index f870859414..bc2abb657c 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -115,6 +115,41 @@ static void enable_per_clocks(void)
while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
;
+ /* UART1 */
+#ifdef CONFIG_SERIAL2
+ writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
+ while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
+ ;
+#endif /* CONFIG_SERIAL2 */
+
+ /* UART2 */
+#ifdef CONFIG_SERIAL3
+ writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
+ while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
+ ;
+#endif /* CONFIG_SERIAL3 */
+
+ /* UART3 */
+#ifdef CONFIG_SERIAL4
+ writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
+ while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
+ ;
+#endif /* CONFIG_SERIAL4 */
+
+ /* UART4 */
+#ifdef CONFIG_SERIAL5
+ writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
+ while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
+ ;
+#endif /* CONFIG_SERIAL5 */
+
+ /* UART5 */
+#ifdef CONFIG_SERIAL6
+ writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
+ while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
+ ;
+#endif /* CONFIG_SERIAL6 */
+
/* MMC0*/
writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 9cee1d9b49..f3cd81ad98 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -50,7 +50,9 @@ DECLARE_GLOBAL_DATA_PTR;
/* Declarations */
extern omap3_sysinfo sysinfo;
static void omap3_setup_aux_cr(void);
+#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_invalidate_l2_cache_secure(void);
+#endif
static const struct gpio_bank gpio_bank_34xx[6] = {
{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -410,19 +412,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
}
}
-static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
-{
- u32 acr;
-
- /* Read ACR */
- asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
- acr &= ~clear_bits;
- acr |= set_bits;
-
- /* Write ACR - affects non-secure banked bits */
- asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
-}
-
static void omap3_setup_aux_cr(void)
{
/* Workaround for Cortex-A8 errata: #454179 #430973
@@ -436,6 +425,19 @@ static void omap3_setup_aux_cr(void)
}
#ifndef CONFIG_SYS_L2CACHE_OFF
+static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
+{
+ u32 acr;
+
+ /* Read ACR */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+ acr &= ~clear_bits;
+ acr |= set_bits;
+
+ /* Write ACR - affects non-secure banked bits */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
+}
+
/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 89df4dc708..78a7facfc3 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -267,3 +267,8 @@ struct meminfo {
extern struct meminfo meminfo;
#endif
+
+/*
+ * Board specified tags
+ */
+void setup_board_tags(struct tag **in_params);
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 37476cc90d..1bd2730856 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -34,6 +34,7 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/bootm.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -269,6 +270,8 @@ static int create_fdt(bootm_headers_t *images)
}
#endif
+__weak void setup_board_tags(struct tag **in_params) {}
+
/* Subcommand: PREP */
static void boot_prep_linux(bootm_headers_t *images)
{
@@ -310,6 +313,7 @@ static void boot_prep_linux(bootm_headers_t *images)
setup_initrd_tag(gd->bd, images->rd_start,
images->rd_end);
#endif
+ setup_board_tags(&params);
setup_end_tag(gd->bd);
#else /* all tags */
printf("FDT and ATAGS support not compiled in - hanging\n");
diff --git a/board/8dtech/eco5pk/Makefile b/board/8dtech/eco5pk/Makefile
new file mode 100644
index 0000000000..befe60aac0
--- /dev/null
+++ b/board/8dtech/eco5pk/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Adapted from ti/evm/Makefile
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := eco5pk.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/8dtech/eco5pk/eco5pk.c b/board/8dtech/eco5pk/eco5pk.c
new file mode 100644
index 0000000000..cdb5b6f67d
--- /dev/null
+++ b/board/8dtech/eco5pk/eco5pk.c
@@ -0,0 +1,61 @@
+/*
+ * eco5pk.c - board file for 8D Technology's AM3517 based eco5pk board
+ *
+ * Based on am3517evm.c
+ *
+ * Copyright (C) 2011-2012 8D Technologies inc.
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <crc.h>
+#include <asm/mach-types.h>
+#include "eco5pk.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ gpio_request(30, "RESOUT");
+ gpio_direction_output(30, 1);
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_ECO5_PK();
+}
diff --git a/board/8dtech/eco5pk/eco5pk.h b/board/8dtech/eco5pk/eco5pk.h
new file mode 100644
index 0000000000..d289e2bf1d
--- /dev/null
+++ b/board/8dtech/eco5pk/eco5pk.h
@@ -0,0 +1,404 @@
+/*
+ * eco5.h - Header file for the 8D Technologies ECO5 board.
+ *
+ * Based on am3517evm.h
+ * Based on ti/evm/evm.h
+ *
+ * Copyright (C) 2011 8D Technologies inc.
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _ECO5PK_H__
+#define _ECO5PK_H__
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "ECO5 Board",
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_ECO5_PK() \
+ /* SDRC */\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_CKE0), (M0)) \
+ MUX_VAL(CP(SDRC_CKE1), (M0)) \
+ MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
+ /* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M3)) \
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
+ /* - ETH_nRESET*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
+ /* DSS */\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
+ /* CAMERA */\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ /* - CAM_RESET*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
+ /* MMC */\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
+ \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \
+ /* McBSP */\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /* LED ACT */ \
+ \
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+ /* - LCD_INI*/\
+ MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+ /* - LCD_ENVDD */\
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+ /* - LCD_QVGA/nVGA */\
+ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+ /* - LCD_RESB */\
+ /* UART */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
+ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
+ /* I2C */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
+ /* McSPI */\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
+ /* - LAN_INTR*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \
+ \
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
+ /* LCD_EN_BACKLIGHT */\
+ MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | EN | M4)) \
+ /* CCDC */\
+ MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
+ /* RMII */\
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
+ MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
+ /* HECC */\
+ MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
+ /* HSUSB */\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
+ /* HDQ */\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
+ /* Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
+ /* SYS_nRESWARM */\
+ MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
+ /* - GPIO30 */\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
+ /* - PEN_IRQ */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /* GPIO_8 */\
+ /* - VIO_1V8*/\
+ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
+ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
+ /* JTAG */\
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
+ /* ETK (ES2 onwards) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \
+ /* Die to Die */\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))
+
+#endif
diff --git a/board/nokia/rx51/Makefile b/board/nokia/rx51/Makefile
new file mode 100644
index 0000000000..86fb48cc99
--- /dev/null
+++ b/board/nokia/rx51/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := $(BOARD).o
+SOBJS-y := lowlevel_init.o
+
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
+SRCS := $(COBJS:.o=.c) $(SOBJS:.o=.S)
+OBJS := $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S
new file mode 100644
index 0000000000..055b1038d1
--- /dev/null
+++ b/board/nokia/rx51/lowlevel_init.S
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+relocaddr: /* address of this relocaddr section after coping */
+ .word . /* address of section (calculated at compile time) */
+
+startaddr: /* address of u-boot after copying */
+ .word CONFIG_SYS_TEXT_BASE
+
+kernaddr: /* address of kernel after copying */
+ .word KERNEL_ADDRESS
+
+kernsize: /* maximal size of kernel image */
+ .word KERNEL_MAXSIZE
+
+kernoffs: /* offset of kernel image in loaded u-boot */
+ .word KERNEL_OFFSET
+
+imagesize: /* maximal size of image */
+ .word IMAGE_MAXSIZE
+
+ih_magic: /* IH_MAGIC in big endian from include/image.h */
+ .word 0x56190527
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: Copy attached kernel to address KERNEL_ADDRESS
+ * Copy u-boot to address CONFIG_SYS_TEXT_BASE
+ * Return to copied u-boot address
+ */
+
+.global save_boot_params
+save_boot_params:
+
+
+/* Copy valid attached kernel to address KERNEL_ADDRESS */
+
+copy_kernel_start:
+ adr r0, relocaddr /* r0 - address of section relocaddr */
+ ldr r1, relocaddr /* r1 - address of relocaddr after relocation */
+ cmp r0, r1
+
+ /* r4 - calculated offset */
+ subhi r4, r0, r1
+ sublo r4, r1, r0
+
+ /* r0 - start of kernel before */
+ ldr r0, startaddr
+ addhi r0, r0, r4
+ sublo r0, r0, r4
+ ldr r1, kernoffs
+ add r0, r0, r1
+
+ /* r3 - start of kernel after */
+ ldr r3, kernaddr
+
+ /* r2 - end of kernel after */
+ ldr r1, kernsize
+ add r2, r3, r1
+
+ /* r1 - end of kernel before */
+ add r1, r0, r1
+
+ /* remove header in target kernel */
+ mov r5, #0
+ str r5, [r3]
+
+ /* check for valid kernel uImage */
+ ldr r4, [r0] /* r4 - 4 bytes header of kernel */
+ ldr r5, ih_magic /* r5 - IH_MAGIC */
+ cmp r4, r5
+ bne copy_kernel_end /* skip if invalid image */
+
+copy_kernel_loop:
+ ldmdb r1!, {r3 - r10}
+ stmdb r2!, {r3 - r10}
+ cmp r1, r0
+ bhi copy_kernel_loop
+
+copy_kernel_end:
+ mov r5, #0
+ str r5, [r0] /* remove 4 bytes header of kernel */
+
+
+/* Fix u-boot code */
+
+fix_start:
+ adr r0, relocaddr /* r0 - address of section relocaddr */
+ ldr r1, relocaddr /* r1 - address of relocaddr after relocation */
+ cmp r0, r1
+
+ beq copy_uboot_end /* skip if u-boot is on correct address */
+
+ /* r5 - calculated offset */
+ subhi r5, r0, r1
+ sublo r5, r1, r0
+
+ /* r6 - maximal u-boot size */
+ ldr r6, imagesize
+
+ /* fix return address */
+ subhi lr, lr, r5
+ addlo lr, lr, r5
+
+ /* r1 - start of u-boot after */
+ ldr r1, startaddr
+
+ /* r0 - start of u-boot before */
+ addhi r0, r1, r5
+ sublo r0, r1, r5
+
+ /* check if we need to move uboot copy code before calling it */
+ cmp r5, r6
+ bhi copy_uboot_start /* now coping u-boot code directly is safe */
+
+
+copy_code_start:
+ /* r0 - start of u-boot before */
+ /* r1 - start of u-boot after */
+ /* r6 - maximal u-boot size */
+
+ /* r7 - maximal kernel size */
+ ldr r7, kernsize
+
+ /* r4 - end of kernel before */
+ add r4, r0, r6
+ add r4, r4, r7
+
+ /* r5 - end of u-boot after */
+ ldr r5, startaddr
+ add r5, r5, r6
+
+ /* r2 - start of loop code after */
+ cmp r4, r5 /* higher address (r4 or r5) */
+ movhs r2, r4
+ movlo r2, r5
+
+ /* r3 - end of loop code before */
+ adr r3, end
+
+ /* r4 - end of loop code after */
+ adr r4, copy_uboot_start
+ sub r4, r3, r4
+ add r4, r2, r4
+
+copy_code_loop:
+ ldmdb r3!, {r7 - r10}
+ stmdb r4!, {r7 - r10}
+ cmp r4, r2
+ bhi copy_code_loop
+
+copy_code_end:
+ mov pc, r2
+
+
+/* Copy u-boot to address CONFIG_SYS_TEXT_BASE */
+
+copy_uboot_start:
+ /* r0 - start of u-boot before */
+ /* r1 - start of u-boot after */
+ /* r6 - maximal u-boot size */
+
+ /* r2 - end of u-boot after */
+ add r2, r1, r6
+
+ /* condition for copying from left to right */
+ cmp r0, r1
+ addlo r1, r0, r6 /* r1 - end of u-boot before */
+ blo copy_uboot_loop_right
+
+copy_uboot_loop_left:
+ ldmia r0!, {r3 - r10}
+ stmia r1!, {r3 - r10}
+ cmp r1, r2
+ blo copy_uboot_loop_left
+ b copy_uboot_end
+
+copy_uboot_loop_right:
+ ldmdb r1!, {r3 - r10}
+ stmdb r2!, {r3 - r10}
+ cmp r1, r0
+ bhi copy_uboot_loop_right
+
+copy_uboot_end:
+ bx lr
+
+end:
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
new file mode 100644
index 0000000000..b2fe1c531a
--- /dev/null
+++ b/board/nokia/rx51/rx51.c
@@ -0,0 +1,677 @@
+/*
+ * (C) Copyright 2012
+ * Ивайло Димитров <freemangordon@abv.bg>
+ *
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2010
+ * Alistair Buxton <a.j.buxton@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code:
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <malloc.h>
+#include <twl4030.h>
+#include <i2c.h>
+#include <video_fb.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/bitops.h>
+#include <asm/mach-types.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "rx51.h"
+#include "tag_omap.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+GraphicDevice gdev;
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "Nokia RX-51",
+ "OneNAND"
+};
+
+/* This structure contains default omap tags needed for booting Maemo 5 */
+static struct tag_omap omap[] = {
+ OMAP_TAG_UART_CONFIG(0x04),
+ OMAP_TAG_SERIAL_CONSOLE_CONFIG(0x03, 0x01C200),
+ OMAP_TAG_LCD_CONFIG("acx565akm", "internal", 90, 0x18),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cam_focus", 0x44, 0x1, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cam_launch", 0x45, 0x1, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cam_shutter", 0x6e, 0x1, 0x0, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_apeslpx", 0x46, 0x2, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_bsi", 0x9d, 0x2, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_en", 0x4a, 0x2, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst", 0x4b, 0x6, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst_rq", 0x49, 0x6, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_wddis", 0x0d, 0x2, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("headphone", 0xb1, 0x1, 0x1, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("kb_lock", 0x71, 0x1, 0x0, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("proximity", 0x59, 0x0, 0x0, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("sleep_ind", 0xa2, 0x2, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("slide", GPIO_SLIDE, 0x0, 0x0, 0x0),
+ OMAP_TAG_WLAN_CX3110X_CONFIG(0x25, 0xff, 87, 42, -1),
+ OMAP_TAG_PARTITION_CONFIG(PART1_NAME, PART1_SIZE * PART1_MULL,
+ PART1_OFFS, PART1_MASK),
+ OMAP_TAG_PARTITION_CONFIG(PART2_NAME, PART2_SIZE * PART2_MULL,
+ PART2_OFFS, PART2_MASK),
+ OMAP_TAG_PARTITION_CONFIG(PART3_NAME, PART3_SIZE * PART3_MULL,
+ PART3_OFFS, PART3_MASK),
+ OMAP_TAG_PARTITION_CONFIG(PART4_NAME, PART4_SIZE * PART4_MULL,
+ PART4_OFFS, PART4_MASK),
+ OMAP_TAG_PARTITION_CONFIG(PART5_NAME, PART5_SIZE * PART5_MULL,
+ PART5_OFFS, PART5_MASK),
+ OMAP_TAG_PARTITION_CONFIG(PART6_NAME, PART6_SIZE * PART6_MULL,
+ PART6_OFFS, PART6_MASK),
+ OMAP_TAG_BOOT_REASON_CONFIG("pwr_key"),
+ OMAP_TAG_VERSION_STR_CONFIG("product", "RX-51"),
+ OMAP_TAG_VERSION_STR_CONFIG("hw-build", "2101"),
+ OMAP_TAG_VERSION_STR_CONFIG("nolo", "1.4.14"),
+ OMAP_TAG_VERSION_STR_CONFIG("boot-mode", "normal"),
+ { }
+};
+
+static char *boot_reason_ptr;
+static char *hw_build_ptr;
+static char *nolo_version_ptr;
+static char *boot_mode_ptr;
+
+/*
+ * Routine: init_omap_tags
+ * Description: Initialize pointers to values in tag_omap
+ */
+static void init_omap_tags(void)
+{
+ char *component;
+ char *version;
+ int i = 0;
+ while (omap[i].hdr.tag) {
+ switch (omap[i].hdr.tag) {
+ case OMAP_TAG_BOOT_REASON:
+ boot_reason_ptr = omap[i].u.boot_reason.reason_str;
+ break;
+ case OMAP_TAG_VERSION_STR:
+ component = omap[i].u.version.component;
+ version = omap[i].u.version.version;
+ if (strcmp(component, "hw-build") == 0)
+ hw_build_ptr = version;
+ else if (strcmp(component, "nolo") == 0)
+ nolo_version_ptr = version;
+ else if (strcmp(component, "boot-mode") == 0)
+ boot_mode_ptr = version;
+ break;
+ default:
+ break;
+ }
+ i++;
+ }
+}
+
+static void reuse_omap_atags(struct tag_omap *t)
+{
+ char *component;
+ char *version;
+ while (t->hdr.tag) {
+ switch (t->hdr.tag) {
+ case OMAP_TAG_BOOT_REASON:
+ memset(boot_reason_ptr, 0, 12);
+ strcpy(boot_reason_ptr, t->u.boot_reason.reason_str);
+ break;
+ case OMAP_TAG_VERSION_STR:
+ component = t->u.version.component;
+ version = t->u.version.version;
+ if (strcmp(component, "hw-build") == 0) {
+ memset(hw_build_ptr, 0, 12);
+ strcpy(hw_build_ptr, version);
+ } else if (strcmp(component, "nolo") == 0) {
+ memset(nolo_version_ptr, 0, 12);
+ strcpy(nolo_version_ptr, version);
+ } else if (strcmp(component, "boot-mode") == 0) {
+ memset(boot_mode_ptr, 0, 12);
+ strcpy(boot_mode_ptr, version);
+ }
+ break;
+ default:
+ break;
+ }
+ t = tag_omap_next(t);
+ }
+}
+
+/*
+ * Routine: reuse_atags
+ * Description: Reuse atags from previous bootloader.
+ * Reuse only only HW build, boot reason, boot mode and nolo
+ */
+static void reuse_atags(void)
+{
+ struct tag *t = (struct tag *)gd->bd->bi_boot_params;
+
+ /* First tag must be ATAG_CORE */
+ if (t->hdr.tag != ATAG_CORE)
+ return;
+
+ if (!boot_reason_ptr || !hw_build_ptr)
+ return;
+
+ /* Last tag must be ATAG_NONE */
+ while (t->hdr.tag != ATAG_NONE) {
+ switch (t->hdr.tag) {
+ case ATAG_REVISION:
+ memset(hw_build_ptr, 0, 12);
+ sprintf(hw_build_ptr, "%x", t->u.revision.rev);
+ break;
+ case ATAG_BOARD:
+ reuse_omap_atags((struct tag_omap *)&t->u);
+ break;
+ default:
+ break;
+ }
+ t = tag_next(t);
+ }
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ /* in SRAM or SDRAM, finish GPMC */
+ gpmc_init();
+ /* boot param addr */
+ gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
+ return 0;
+}
+
+/*
+ * Routine: get_board_revision
+ * Description: Return board revision.
+ */
+u32 get_board_rev(void)
+{
+ return simple_strtol(hw_build_ptr, NULL, 16);
+}
+
+/*
+ * Routine: setup_board_tags
+ * Description: Append board specific boot tags.
+ */
+void setup_board_tags(struct tag **in_params)
+{
+ int setup_console_atag;
+ char *setup_boot_reason_atag;
+ char *setup_boot_mode_atag;
+ char *str;
+ int i;
+ int size;
+ int total_size;
+ struct tag *params;
+ struct tag_omap *t;
+
+ params = (struct tag *)gd->bd->bi_boot_params;
+
+ params->u.core.flags = 0x0;
+ params->u.core.pagesize = 0x1000;
+ params->u.core.rootdev = 0x0;
+
+ /* append omap atag only if env setup_omap_atag is set to 1 */
+ str = getenv("setup_omap_atag");
+ if (!str || str[0] != '1')
+ return;
+
+ str = getenv("setup_console_atag");
+ if (str && str[0] == '1')
+ setup_console_atag = 1;
+ else
+ setup_console_atag = 0;
+
+ setup_boot_reason_atag = getenv("setup_boot_reason_atag");
+ setup_boot_mode_atag = getenv("setup_boot_mode_atag");
+
+ params = *in_params;
+ t = (struct tag_omap *)&params->u;
+ total_size = sizeof(struct tag_header);
+
+ for (i = 0; omap[i].hdr.tag; i++) {
+
+ /* skip serial console tag */
+ if (!setup_console_atag &&
+ omap[i].hdr.tag == OMAP_TAG_SERIAL_CONSOLE)
+ continue;
+
+ size = omap[i].hdr.size + sizeof(struct tag_omap_header);
+ memcpy(t, &omap[i], size);
+
+ /* set uart tag to 0 - disable serial console */
+ if (!setup_console_atag && omap[i].hdr.tag == OMAP_TAG_UART)
+ t->u.uart.enabled_uarts = 0;
+
+ /* change boot reason */
+ if (setup_boot_reason_atag &&
+ omap[i].hdr.tag == OMAP_TAG_BOOT_REASON) {
+ memset(t->u.boot_reason.reason_str, 0, 12);
+ strcpy(t->u.boot_reason.reason_str,
+ setup_boot_reason_atag);
+ }
+
+ /* change boot mode */
+ if (setup_boot_mode_atag &&
+ omap[i].hdr.tag == OMAP_TAG_VERSION_STR &&
+ strcmp(omap[i].u.version.component, "boot-mode") == 0) {
+ memset(t->u.version.version, 0, 12);
+ strcpy(t->u.version.version, setup_boot_mode_atag);
+ }
+
+ total_size += size;
+ t = tag_omap_next(t);
+
+ }
+
+ params->hdr.tag = ATAG_BOARD;
+ params->hdr.size = total_size >> 2;
+ params = tag_next(params);
+
+ *in_params = params;
+}
+
+/*
+ * Routine: video_hw_init
+ * Description: Set up the GraphicDevice depending on sys_boot.
+ */
+void *video_hw_init(void)
+{
+ /* fill in Graphic Device */
+ gdev.frameAdrs = 0x8f9c0000;
+ gdev.winSizeX = 800;
+ gdev.winSizeY = 480;
+ gdev.gdfBytesPP = 2;
+ gdev.gdfIndex = GDF_16BIT_565RGB;
+ memset((void *)gdev.frameAdrs, 0, 0xbb800);
+ return (void *) &gdev;
+}
+
+/*
+ * Routine: twl4030_regulator_set_mode
+ * Description: Set twl4030 regulator mode over i2c powerbus.
+ */
+static void twl4030_regulator_set_mode(u8 id, u8 mode)
+{
+ u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg >> 8,
+ TWL4030_PM_MASTER_PB_WORD_MSB);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg & 0xff,
+ TWL4030_PM_MASTER_PB_WORD_LSB);
+}
+
+static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
+{
+ u32 i, num_params = *parameters;
+ u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
+
+ /*
+ * copy the parameters to an un-cached area to avoid coherency
+ * issues
+ */
+ for (i = 0; i < num_params; i++) {
+ __raw_writel(*parameters, sram_scratch_space);
+ parameters++;
+ sram_scratch_space++;
+ }
+
+ /* Now make the PPA call */
+ do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
+}
+
+/*
+ * Routine: omap3_update_aux_cr_secure_rx51
+ * Description: Modify the contents Auxiliary Control Register.
+ * Parameters:
+ * set_bits - bits to set in ACR
+ * clr_bits - bits to clear in ACR
+ */
+static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
+{
+ struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+ u32 acr;
+
+ /* Read ACR */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+ acr &= ~clear_bits;
+ acr |= set_bits;
+
+ emu_romcode_params.num_params = 2;
+ emu_romcode_params.param1 = acr;
+
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)&emu_romcode_params);
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts.
+ */
+int misc_init_r(void)
+{
+ char buf[12];
+ u8 state;
+
+ /* reset lp5523 led */
+ i2c_set_bus_num(1);
+ state = 0xff;
+ i2c_write(0x32, 0x3d, 1, &state, 1);
+ i2c_set_bus_num(0);
+
+ /* initialize twl4030 power managment */
+ twl4030_power_init();
+
+ /* set VSIM to 1.8V */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
+ TWL4030_PM_RECEIVER_VSIM_VSEL_18,
+ TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+ /* store I2C access state */
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &state,
+ TWL4030_PM_MASTER_PB_CFG);
+
+ /* enable I2C access to powerbus (needed for twl4030 regulator) */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x02,
+ TWL4030_PM_MASTER_PB_CFG);
+
+ /* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */
+ twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE);
+ twl4030_regulator_set_mode(RES_VSIM, RES_STATE_ACTIVE);
+ twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE);
+
+ /* restore I2C access state */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, state,
+ TWL4030_PM_MASTER_PB_CFG);
+
+ /* set env variable attkernaddr for relocated kernel */
+ sprintf(buf, "%#x", KERNEL_ADDRESS);
+ setenv("attkernaddr", buf);
+
+ /* initialize omap tags */
+ init_omap_tags();
+
+ /* reuse atags from previous bootloader */
+ reuse_atags();
+
+ dieid_num_r();
+ print_cpuinfo();
+
+ /*
+ * Cortex-A8(r1p0..r1p2) errata 430973 workaround
+ * Set IBE bit in Auxiliary Control Register
+ */
+ omap3_update_aux_cr_secure_rx51(1 << 6, 0);
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_RX51();
+}
+
+static unsigned long int twl_wd_time; /* last time of watchdog reset */
+static unsigned long int twl_i2c_lock;
+
+/*
+ * Routine: hw_watchdog_reset
+ * Description: Reset timeout of twl4030 watchdog.
+ */
+void hw_watchdog_reset(void)
+{
+ u8 timeout = 0;
+
+ /* do not reset watchdog too often - max every 4s */
+ if (get_timer(twl_wd_time) < 4 * CONFIG_SYS_HZ)
+ return;
+
+ /* localy lock twl4030 i2c bus */
+ if (test_and_set_bit(0, &twl_i2c_lock))
+ return;
+
+ /* read actual watchdog timeout */
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &timeout,
+ TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+
+ /* timeout 0 means watchdog is disabled */
+ /* reset watchdog timeout to 31s (maximum) */
+ if (timeout != 0)
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 31,
+ TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+
+ /* store last watchdog reset time */
+ twl_wd_time = get_timer(0);
+
+ /* localy unlock twl4030 i2c bus */
+ test_and_clear_bit(0, &twl_i2c_lock);
+}
+
+/*
+ * TWL4030 keypad handler for cfb_console
+ */
+
+static const char keymap[] = {
+ /* normal */
+ 'q', 'o', 'p', ',', '\b', 0, 'a', 's',
+ 'w', 'd', 'f', 'g', 'h', 'j', 'k', 'l',
+ 'e', '.', 0, '\r', 0, 'z', 'x', 'c',
+ 'r', 'v', 'b', 'n', 'm', ' ', ' ', 0,
+ 't', 0, 0, 0, 0, 0, 0, 0,
+ 'y', 0, 0, 0, 0, 0, 0, 0,
+ 'u', 0, 0, 0, 0, 0, 0, 0,
+ 'i', 5, 6, 0, 0, 0, 0, 0,
+ /* fn */
+ '1', '9', '0', '=', '\b', 0, '*', '+',
+ '2', '#', '-', '_', '(', ')', '&', '!',
+ '3', '?', '^', '\r', 0, 156, '$', 238,
+ '4', '/', '\\', '"', '\'', '@', 0, '<',
+ '5', '|', '>', 0, 0, 0, 0, 0,
+ '6', 0, 0, 0, 0, 0, 0, 0,
+ '7', 0, 0, 0, 0, 0, 0, 0,
+ '8', 16, 17, 0, 0, 0, 0, 0,
+};
+
+static u8 keys[8];
+static u8 old_keys[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+#define KEYBUF_SIZE 32
+static u8 keybuf[KEYBUF_SIZE];
+static u8 keybuf_head;
+static u8 keybuf_tail;
+
+/*
+ * Routine: rx51_kp_init
+ * Description: Initialize HW keyboard.
+ */
+int rx51_kp_init(void)
+{
+ int ret = 0;
+ u8 ctrl;
+ ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl,
+ TWL4030_KEYPAD_KEYP_CTRL_REG);
+
+ if (ret)
+ return ret;
+
+ /* turn on keyboard and use hardware scanning */
+ ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON;
+ ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST;
+ ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN;
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl,
+ TWL4030_KEYPAD_KEYP_CTRL_REG);
+ /* enable key event status */
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0xfe,
+ TWL4030_KEYPAD_KEYP_IMR1);
+ /* enable interrupt generation on rising and falling */
+ /* this is a workaround for qemu twl4030 emulation */
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x57,
+ TWL4030_KEYPAD_KEYP_EDR);
+ /* enable ISR clear on read */
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x05,
+ TWL4030_KEYPAD_KEYP_SIH_CTRL);
+ return 0;
+}
+
+static void rx51_kp_fill(u8 k, u8 mods)
+{
+ /* check if some cursor key without meta fn key was pressed */
+ if (!(mods & 2) && (k == 18 || k == 31 || k == 33 || k == 34)) {
+ keybuf[keybuf_tail++] = '\e';
+ keybuf_tail %= KEYBUF_SIZE;
+ keybuf[keybuf_tail++] = '[';
+ keybuf_tail %= KEYBUF_SIZE;
+ if (k == 18) /* up */
+ keybuf[keybuf_tail++] = 'A';
+ else if (k == 31) /* left */
+ keybuf[keybuf_tail++] = 'D';
+ else if (k == 33) /* down */
+ keybuf[keybuf_tail++] = 'B';
+ else if (k == 34) /* right */
+ keybuf[keybuf_tail++] = 'C';
+ keybuf_tail %= KEYBUF_SIZE;
+ return;
+ }
+
+ if (mods & 2) { /* fn meta key was pressed */
+ k = keymap[k+64];
+ } else {
+ k = keymap[k];
+ if (mods & 1) { /* ctrl key was pressed */
+ if (k >= 'a' && k <= 'z')
+ k -= 'a' - 1;
+ }
+ if (mods & 4) { /* shift key was pressed */
+ if (k >= 'a' && k <= 'z')
+ k += 'A' - 'a';
+ else if (k == '.')
+ k = ':';
+ else if (k == ',')
+ k = ';';
+ }
+ }
+ keybuf[keybuf_tail++] = k;
+ keybuf_tail %= KEYBUF_SIZE;
+}
+
+/*
+ * Routine: rx51_kp_tstc
+ * Description: Test if key was pressed (from buffer).
+ */
+int rx51_kp_tstc(void)
+{
+ u8 c, r, dk, i;
+ u8 intr;
+ u8 mods;
+
+ /* localy lock twl4030 i2c bus */
+ if (test_and_set_bit(0, &twl_i2c_lock))
+ return 0;
+
+ /* twl4030 remembers up to 2 events */
+ for (i = 0; i < 2; i++) {
+
+ /* check interrupt register for events */
+ twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &intr,
+ TWL4030_KEYPAD_KEYP_ISR1+(2*i));
+
+ /* no event */
+ if (!(intr&1))
+ continue;
+
+ /* read the key state */
+ i2c_read(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_FULL_CODE_7_0, 1, keys, 8);
+
+ /* cut out modifier keys from the keystate */
+ mods = keys[4] >> 4;
+ keys[4] &= 0x0f;
+
+ for (c = 0; c < 8; c++) {
+
+ /* get newly pressed keys only */
+ dk = ((keys[c] ^ old_keys[c])&keys[c]);
+ old_keys[c] = keys[c];
+
+ /* fill the keybuf */
+ for (r = 0; r < 8; r++) {
+ if (dk&1)
+ rx51_kp_fill((c*8)+r, mods);
+ dk = dk >> 1;
+ }
+
+ }
+
+ }
+
+ /* localy unlock twl4030 i2c bus */
+ test_and_clear_bit(0, &twl_i2c_lock);
+
+ return (KEYBUF_SIZE + keybuf_tail - keybuf_head)%KEYBUF_SIZE;
+}
+
+/*
+ * Routine: rx51_kp_getc
+ * Description: Get last pressed key (from buffer).
+ */
+int rx51_kp_getc(void)
+{
+ keybuf_head %= KEYBUF_SIZE;
+ while (!rx51_kp_tstc())
+ WATCHDOG_RESET();
+ return keybuf[keybuf_head++];
+}
+
+/*
+ * Routine: board_mmc_init
+ * Description: Initialize mmc devices.
+ */
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0);
+ omap_mmc_init(1, 0, 0);
+ return 0;
+}
diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h
new file mode 100644
index 0000000000..e66e241488
--- /dev/null
+++ b/board/nokia/rx51/rx51.h
@@ -0,0 +1,389 @@
+/*
+ * (C) Copyright 2012
+ * Ивайло Димитров <freemangordon@abv.bg>
+ *
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _RX51_H_
+#define _RX51_H_
+
+/* Needed for ROM SMC call */
+struct emu_hal_params_rx51 {
+ u32 num_params;
+ u32 param1;
+ u32 param2;
+ u32 param3;
+ u32 param4;
+};
+
+int print_cpuinfo(void);
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_RX51() \
+/* SDRC */\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+/* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*nDMA_REQ2*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*nDMA_REQ3*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+/* DSS */\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+/* CAMERA */\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS*/\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS*/\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+/* Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLK*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+/* Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+/* Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+/* Bluetooth */\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
+/* Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT*/\
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG*/\
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY*/\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+/* Serial Interface */\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOM*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+/* USB EHCI (port 2) */\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DA2*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DA5*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DA6*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DA3*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA0*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA1*/\
+/* Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*MMC1_WP*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MD*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26m*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespw*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswa*/\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9ni*/\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmare0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmare1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmare2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmare3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrs*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtc*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeu*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlere*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleac*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusfl*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusfl*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#define MUX_RX51_C() \
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
+
+#endif
diff --git a/board/nokia/rx51/tag_omap.h b/board/nokia/rx51/tag_omap.h
new file mode 100644
index 0000000000..60fa26f3e1
--- /dev/null
+++ b/board/nokia/rx51/tag_omap.h
@@ -0,0 +1,311 @@
+/*
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2011
+ * marcel@mesa.nl, Mesa Consulting B.V.
+ *
+ * (C) Copyright 2004-2005
+ * Nokia Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*
+ * Code copied from maemo kernel 2.6.28 file
+ * arch/arm/plat-omap/include/mach/board.h
+ *
+ * Information structures for board-specific data
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+
+/* Different peripheral ids */
+#define OMAP_TAG_CLOCK 0x4f01
+#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
+#define OMAP_TAG_USB 0x4f04
+#define OMAP_TAG_LCD 0x4f05
+#define OMAP_TAG_GPIO_SWITCH 0x4f06
+#define OMAP_TAG_UART 0x4f07
+#define OMAP_TAG_FBMEM 0x4f08
+#define OMAP_TAG_STI_CONSOLE 0x4f09
+#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
+#define OMAP_TAG_PARTITION 0x4f0b
+#define OMAP_TAG_TEA5761 0x4f10
+#define OMAP_TAG_TMP105 0x4f11
+
+#define OMAP_TAG_BOOT_REASON 0x4f80
+#define OMAP_TAG_FLASH_PART_STR 0x4f81
+#define OMAP_TAG_VERSION_STR 0x4f82
+
+#define OMAP_TAG_NOKIA_BT 0x4e01
+#define OMAP_TAG_WLAN_CX3110X 0x4e02
+#define OMAP_TAG_CBUS 0x4e03
+#define OMAP_TAG_EM_ASIC_BB5 0x4e04
+
+
+struct omap_clock_config {
+ /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
+ u8 system_clock_type;
+};
+
+struct omap_serial_console_config {
+ u8 console_uart;
+ u32 console_speed;
+};
+
+struct omap_sti_console_config {
+ unsigned enable:1;
+ u8 channel;
+};
+
+struct omap_usb_config {
+ /* Configure drivers according to the connectors on your board:
+ * - "A" connector (rectagular)
+ * ... for host/OHCI use, set "register_host".
+ * - "B" connector (squarish) or "Mini-B"
+ * ... for device/gadget use, set "register_dev".
+ * - "Mini-AB" connector (very similar to Mini-B)
+ * ... for OTG use as device OR host, initialize "otg"
+ */
+ unsigned register_host:1;
+ unsigned register_dev:1;
+ u8 otg; /* port number, 1-based: usb1 == 2 */
+
+ u8 hmc_mode;
+
+ /* implicitly true if otg: host supports remote wakeup? */
+ u8 rwc;
+
+ /* signaling pins used to talk to transceiver on usbN:
+ * 0 == usbN unused
+ * 2 == usb0-only, using internal transceiver
+ * 3 == 3 wire bidirectional
+ * 4 == 4 wire bidirectional
+ * 6 == 6 wire unidirectional (or TLL)
+ */
+ u8 pins[3];
+};
+
+struct omap_lcd_config {
+ char panel_name[16];
+ char ctrl_name[16];
+ s16 nreset_gpio;
+ u8 data_lines;
+};
+
+struct omap_fbmem_config {
+ u32 start;
+ u32 size;
+};
+
+struct omap_gpio_switch_config {
+ char name[12];
+ u16 gpio;
+ u8 flags:4;
+ u8 type:4;
+ unsigned int key_code:24; /* Linux key code */
+};
+
+struct omap_uart_config {
+ /* Bit field of UARTs present; bit 0 --> UART1 */
+ unsigned int enabled_uarts;
+};
+
+struct omap_tea5761_config {
+ u16 enable_gpio;
+};
+
+struct omap_partition_config {
+ char name[16];
+ unsigned int size;
+ unsigned int offset;
+ /* same as in include/linux/mtd/partitions.h */
+ unsigned int mask_flags;
+};
+
+struct omap_flash_part_str_config {
+ char part_table[0];
+};
+
+struct omap_boot_reason_config {
+ char reason_str[12];
+};
+
+struct omap_version_config {
+ char component[12];
+ char version[12];
+};
+
+/*
+ * Code copied from maemo kernel 2.6.28 file
+ * arch/arm/plat-omap/include/mach/board-nokia.h
+ *
+ * Information structures for Nokia-specific board config data
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ */
+
+struct omap_bluetooth_config {
+ u8 chip_type;
+ u8 bt_wakeup_gpio;
+ u8 host_wakeup_gpio;
+ u8 reset_gpio;
+ u8 bt_uart;
+ u8 bd_addr[6];
+ u8 bt_sysclk;
+};
+
+struct omap_wlan_cx3110x_config {
+ u8 chip_type;
+ u8 reserverd;
+ s16 power_gpio;
+ s16 irq_gpio;
+ s16 spi_cs_gpio;
+};
+
+struct omap_cbus_config {
+ s16 clk_gpio;
+ s16 dat_gpio;
+ s16 sel_gpio;
+};
+
+struct omap_em_asic_bb5_config {
+ s16 retu_irq_gpio;
+ s16 tahvo_irq_gpio;
+};
+
+/*
+ * omap_tag handling
+ *
+ * processing omap tag structures
+ *
+ * Copyright (C) 2011 marcel@mesa.nl, Mesa Consulting B.V.
+ * Copyright (C) 2012 Pali Rohár <pali.rohar@gmail.com>
+ */
+
+/* TI OMAP specific information */
+#define ATAG_BOARD 0x414f4d50
+
+struct tag_omap_header {
+ u16 tag;
+ u16 size;
+};
+
+struct tag_omap {
+ struct tag_omap_header hdr;
+ union {
+ struct omap_clock_config clock;
+ struct omap_serial_console_config serial_console;
+ struct omap_sti_console_config sti_console;
+ struct omap_usb_config usb;
+ struct omap_lcd_config lcd;
+ struct omap_fbmem_config fbmem;
+ struct omap_gpio_switch_config gpio_switch;
+ struct omap_uart_config uart;
+ struct omap_tea5761_config tea5761;
+ struct omap_partition_config partition;
+ struct omap_flash_part_str_config flash_part_str;
+ struct omap_boot_reason_config boot_reason;
+ struct omap_version_config version;
+ struct omap_bluetooth_config bluetooth;
+ struct omap_wlan_cx3110x_config wlan_cx3110x;
+ struct omap_cbus_config cbus;
+ struct omap_em_asic_bb5_config em_asic_bb5;
+ } u;
+};
+
+#define tag_omap_next(t) ((struct tag_omap *)((u8 *)(t) + \
+ (t)->hdr.size + sizeof(struct tag_omap_header)))
+
+#define OMAP_TAG_HEADER_CONFIG(config, type) \
+ .hdr.tag = config, \
+ .hdr.size = sizeof(struct type)
+
+#define OMAP_TAG_UART_CONFIG(p1) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_UART, omap_uart_config), \
+ .u.uart.enabled_uarts = p1, \
+ }
+
+#define OMAP_TAG_SERIAL_CONSOLE_CONFIG(p1, p2) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_SERIAL_CONSOLE, \
+ omap_serial_console_config), \
+ .u.serial_console.console_uart = p1, \
+ .u.serial_console.console_speed = p2, \
+ }
+
+#define OMAP_TAG_LCD_CONFIG(p1, p2, p3, p4) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_LCD, omap_lcd_config), \
+ .u.lcd.panel_name = p1, \
+ .u.lcd.ctrl_name = p2, \
+ .u.lcd.nreset_gpio = p3, \
+ .u.lcd.data_lines = p4, \
+ }
+
+#define OMAP_TAG_GPIO_SWITCH_CONFIG(p1, p2, p3, p4, p5) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_GPIO_SWITCH, \
+ omap_gpio_switch_config), \
+ .u.gpio_switch.name = p1, \
+ .u.gpio_switch.gpio = p2, \
+ .u.gpio_switch.flags = p3, \
+ .u.gpio_switch.type = p4, \
+ .u.gpio_switch.key_code = p5, \
+ }
+
+#define OMAP_TAG_WLAN_CX3110X_CONFIG(p1, p2, p3, p4, p5) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_WLAN_CX3110X, \
+ omap_wlan_cx3110x_config), \
+ .u.wlan_cx3110x.chip_type = p1, \
+ .u.wlan_cx3110x.reserverd = p2, \
+ .u.wlan_cx3110x.power_gpio = p3, \
+ .u.wlan_cx3110x.irq_gpio = p4, \
+ .u.wlan_cx3110x.spi_cs_gpio = p5, \
+ }
+
+#define OMAP_TAG_PARTITION_CONFIG(p1, p2, p3, p4) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_PARTITION, \
+ omap_partition_config), \
+ .u.partition.name = p1, \
+ .u.partition.size = p2, \
+ .u.partition.offset = p3, \
+ .u.partition.mask_flags = p4, \
+ }
+
+#define OMAP_TAG_BOOT_REASON_CONFIG(p1) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_BOOT_REASON, \
+ omap_boot_reason_config), \
+ .u.boot_reason.reason_str = p1, \
+ }
+
+#define OMAP_TAG_VERSION_STR_CONFIG(p1, p2) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_VERSION_STR, \
+ omap_version_config), \
+ .u.version.component = p1, \
+ .u.version.version = p2, \
+ }
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 5d279ecdbc..e5ad76e9a0 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -68,6 +68,11 @@ static inline int board_is_evm_sk(void)
return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
}
+static inline int board_is_idk(void)
+{
+ return !strncmp(header.config, "SKU#02", 6);
+}
+
/*
* Read header information from EEPROM into global structure.
*/
@@ -242,7 +247,24 @@ void s_init(void)
/* UART softreset */
u32 regVal;
+#ifdef CONFIG_SERIAL1
enable_uart0_pin_mux();
+#endif /* CONFIG_SERIAL1 */
+#ifdef CONFIG_SERIAL2
+ enable_uart1_pin_mux();
+#endif /* CONFIG_SERIAL2 */
+#ifdef CONFIG_SERIAL3
+ enable_uart2_pin_mux();
+#endif /* CONFIG_SERIAL3 */
+#ifdef CONFIG_SERIAL4
+ enable_uart3_pin_mux();
+#endif /* CONFIG_SERIAL4 */
+#ifdef CONFIG_SERIAL5
+ enable_uart4_pin_mux();
+#endif /* CONFIG_SERIAL5 */
+#ifdef CONFIG_SERIAL6
+ enable_uart5_pin_mux();
+#endif /* CONFIG_SERIAL6 */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
@@ -361,7 +383,7 @@ int board_eth_init(bd_t *bis)
return -1;
}
- if (board_is_bone() || board_is_bone_lt()) {
+ if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index 7985ab2c14..48e112e230 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -44,6 +44,11 @@ struct am335x_baseboard_id {
* is required on the board.
*/
void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(struct am335x_baseboard_id *header);
#endif
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 29929791fc..8437ef515a 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -27,6 +27,36 @@ static struct module_pin_mux uart0_pin_mux[] = {
{-1},
};
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
+ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+ {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
+ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
+ {-1},
+};
+
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
@@ -39,6 +69,17 @@ static struct module_pin_mux mmc0_pin_mux[] = {
{-1},
};
+static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
+ {-1},
+};
+
static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
@@ -135,6 +176,30 @@ void enable_uart0_pin_mux(void)
configure_module_pin_mux(uart0_pin_mux);
}
+void enable_uart1_pin_mux(void)
+{
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+ configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+ configure_module_pin_mux(uart5_pin_mux);
+}
void enable_i2c0_pin_mux(void)
{
@@ -196,12 +261,27 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
configure_module_pin_mux(mmc1_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
}
+ } else if (!strncmp(header->config, "SKU#02", 6)) {
+ /*
+ * Industrial Motor Control (IDK)
+ * note: IDK console is on UART3 by default.
+ * So u-boot mus be build with CONFIG_SERIAL4 and
+ * CONFIG_CONS_INDEX=4
+ */
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mmc0_no_cd_pin_mux);
} else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
/* Starter Kit EVM */
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(gpio0_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux_sk_evm);
+ } else if (!strncmp(header->name, "A335BNLT", HDR_NAME_LEN)) {
+ /* Beaglebone LT pinmux */
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
} else {
puts("Unknown board, cannot configure pinmux.");
hang();
diff --git a/boards.cfg b/boards.cfg
index c45556e8fd..25c53d40d2 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -225,7 +225,12 @@ versatileqemu arm arm926ejs versatile armltd
integratorap_cm946es arm arm946es integrator armltd - integratorap:CM946ES
integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES
ca9x4_ct_vxp arm armv7 vexpress armltd
-am335x_evm arm armv7 am335x ti am33xx
+am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1
+am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2
+am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3
+am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4
+am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5
+am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6
highbank arm armv7 highbank - highbank
mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
@@ -240,6 +245,7 @@ mx6qarm2 arm armv7 mx6qarm2 freesca
mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+eco5pk arm armv7 eco5pk 8dtech omap3
cm_t35 arm armv7 cm_t35 - omap3
omap3_overo arm armv7 overo - omap3
omap3_pandora arm armv7 pandora - omap3
@@ -264,6 +270,7 @@ devkit8000 arm armv7 devkit8000 timll
mcx arm armv7 mcx htkw omap3
tricorder arm armv7 tricorder corscience omap3
twister arm armv7 twister technexion omap3
+nokia_rx51 arm armv7 rx51 nokia omap3
omap4_panda arm armv7 panda ti omap4
omap4_sdp4430 arm armv7 sdp4430 ti omap4
omap5_evm arm armv7 omap5_evm ti omap5
diff --git a/doc/README.nokia_rx51 b/doc/README.nokia_rx51
new file mode 100644
index 0000000000..a8fdfcd372
--- /dev/null
+++ b/doc/README.nokia_rx51
@@ -0,0 +1,104 @@
+Board: Nokia RX-51 aka N900
+
+This board definition results in a u-boot.bin which can be chainloaded
+from NOLO in qemu or on a real N900. It does very little hardware config
+because NOLO has already configured the board. Only needed is enabling
+internal eMMC memory via twl4030 regulator which is not enabled by NOLO.
+
+NOLO is expecting a kernel image and will treat any image it finds in
+onenand as such. This u-boot is intended to be flashed to the N900 like
+a kernel. In order to transparently boot the original kernel, it will be
+appended to u-boot.bin at 0x40000. NOLO will load the entire image into
+(random) memory and execute u-boot, which saves hw revision, boot reason
+and boot mode ATAGs set by NOLO. Then the bootscripts will attempt to load
+uImage or boot.scr from a fat, ext2/ext3 or ext4 filesystem in external
+SD card or internal eMMC memory. If this fails or keyboard is closed then
+the appended kernel image will be booted using some generated and some
+stored ATAGs (see boot order).
+
+There is support for hardware watchdog. Hardware watchdog is started by
+NOLO so u-boot must kick watchdog to prevent reboot device (but not very
+often, max every 2 seconds). There is also support for framebuffer display
+output with ANSI espace codes and the N900 HW keyboard input. USB tty works
+but is disabled because it prevents the current Maemo kernel from booting.
+
+When U-Boot is starting it enable IBE bit in Auxiliary Control Register,
+which is needed for Thumb-2 ISA support. It is workaround for errata 430973.
+
+Default boot order:
+
+ * 0. if keyboard is closed boot automatically attached kernel image
+ * 1. try boot from external SD card
+ * 2. try boot from internal eMMC memory
+ * 3. try boot from attached kernel image
+
+Boot from SD or eMMC in this order:
+
+ * 1.
+ * 1.1 find boot.scr on first fat partition
+ * 1.2 find uImage on first fat parition
+ * 1.3 same order for 2. - 4. fat partition
+ * 2. same as 1. but for ext2/3 partition
+ * 3. same as 1. but for ext4 partition
+
+
+Available additional commands/variables:
+
+ * run sercon - Use serial port for control
+ * run usbcon - Use usbtty for control
+ * run vgacon - Use framebuffer and HW keyboard for control (default)
+
+ * run sdboot - Boot from external SD card (see boot order)
+ * run emmcboot - Boot from internal eMMC memory (see boot order)
+ * run attachboot - Boot attached kernel image (attached to U-Boot binary)
+
+ * run scriptload - Load boot script ${mmcscriptfile}
+ * run scriptboot - Run loaded boot script
+ * run kernload - Load kernel image ${mmckernfile}
+ * run initrdload - Load initrd image ${mmcinitrdfile}
+ * run kernboot - Boot loaded kernel image
+ * run kerninitrdboot - Boot loaded kernel image with loaded initrd image
+
+ * run trymmcscriptboot - Try to load and boot script ${mmcscriptfile}
+ * run trymmckernboot - Try to load and boot kernel image ${mmckernfile}
+ * run trymmckerninitrdboot - Try to load and boot kernel image ${mmckernfile}
+ with initrd image ${mmcinitrdfile}
+
+Additional variables for loading files from mmc:
+
+ * mmc ${mmcnum} (0 - external, 1 - internal)
+ * partition number ${mmcpart} (1 - 4)
+ * parition type ${mmctype} (fat, ext2)
+
+Additional varuables for booting kernel:
+
+ * setup_omap_atag - Add OMAP table into atags structure (needs maemo kernel)
+ * setup_console_atag - Enable serial console in OMAP table
+ * setup_boot_reason_atag - Change boot reason in OMAP table
+ * setup_boot_mode_atag - Change boot mode in OMAP table
+
+USB TTY:
+
+ Maemo kernel 2.6.28 will crash if u-boot enable usb tty. So USB TTY is disabled.
+ For enabling USB TTY just add this line to file include/configs/nokia_rx51.h
+
+ #define CONFIG_USB_TTY
+
+
+ONENAND support:
+
+ ONENAND support is disabled because not working yet and cause linux kernel to
+ crash or no access to mtd. For enabling ONENAND support add this line at begin
+ of file include/configs/nokia_rx51.h
+
+ #define ONENAND_SUPPORT
+
+
+UBIFS support:
+
+ UBIFS support is disabled, because U-Boot image is too big and cannot be
+ flashed with attached zImage to RX-51 kernel nand area. For enabling UBIFS
+ support first enable ONENAND support and then add this line at begin of file
+ include/configs/nokia_rx51.h
+
+ #define UBIFS_SUPPORT
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index b5d12481ca..5fb38410a8 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_CONS_INDEX)
-#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
+#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6)
#error "Invalid console index value."
#endif
@@ -46,12 +46,16 @@ DECLARE_GLOBAL_DATA_PTR;
#error "Console port 3 defined but not configured."
#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
#error "Console port 4 defined but not configured."
+#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
+#error "Console port 5 defined but not configured."
+#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
+#error "Console port 6 defined but not configured."
#endif
/* Note: The port number specified in the functions is 1 based.
* the array is 0 based.
*/
-static NS16550_t serial_ports[4] = {
+static NS16550_t serial_ports[6] = {
#ifdef CONFIG_SYS_NS16550_COM1
(NS16550_t)CONFIG_SYS_NS16550_COM1,
#else
@@ -68,7 +72,17 @@ static NS16550_t serial_ports[4] = {
NULL,
#endif
#ifdef CONFIG_SYS_NS16550_COM4
- (NS16550_t)CONFIG_SYS_NS16550_COM4
+ (NS16550_t)CONFIG_SYS_NS16550_COM4,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_NS16550_COM5
+ (NS16550_t)CONFIG_SYS_NS16550_COM5,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_NS16550_COM6
+ (NS16550_t)CONFIG_SYS_NS16550_COM6
#else
NULL
#endif
@@ -231,6 +245,12 @@ struct serial_device eserial3_device =
DECLARE_ESERIAL_FUNCTIONS(4);
struct serial_device eserial4_device =
INIT_ESERIAL_STRUCTURE(4, "eserial3");
+DECLARE_ESERIAL_FUNCTIONS(5);
+struct serial_device eserial5_device =
+ INIT_ESERIAL_STRUCTURE(5, "eserial4");
+DECLARE_ESERIAL_FUNCTIONS(6);
+struct serial_device eserial6_device =
+ INIT_ESERIAL_STRUCTURE(6, "eserial5");
__weak struct serial_device *default_serial_console(void)
{
@@ -242,6 +262,10 @@ __weak struct serial_device *default_serial_console(void)
return &eserial3_device;
#elif CONFIG_CONS_INDEX == 4
return &eserial4_device;
+#elif CONFIG_CONS_INDEX == 5
+ return &eserial5_device;
+#elif CONFIG_CONS_INDEX == 6
+ return &eserial6_device;
#else
#error "Bad CONFIG_CONS_INDEX."
#endif
@@ -261,4 +285,10 @@ void ns16550_serial_initialize(void)
#if defined(CONFIG_SYS_NS16550_COM4)
serial_register(&eserial4_device);
#endif
+#if defined(CONFIG_SYS_NS16550_COM5)
+ serial_register(&eserial5_device);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM6)
+ serial_register(&eserial6_device);
+#endif
}
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 9f7794fe53..9c67b63bf4 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -385,6 +385,13 @@ static u32 eorx, fgx, bgx; /* color pats */
static int cfb_do_flush_cache;
+#ifdef CONFIG_CFB_CONSOLE_ANSI
+static char ansi_buf[10];
+static int ansi_buf_size;
+static int ansi_colors_need_revert;
+static int ansi_cursor_hidden;
+#endif
+
static const int video_font_draw_table8[] = {
0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
@@ -768,9 +775,97 @@ static void console_back(void)
}
}
-static void console_newline(void)
+#ifdef CONFIG_CFB_CONSOLE_ANSI
+
+static void console_clear(void)
+{
+#ifdef VIDEO_HW_RECTFILL
+ video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */
+ 0, /* dest pos x */
+ video_logo_height, /* dest pos y */
+ VIDEO_VISIBLE_COLS, /* frame width */
+ VIDEO_VISIBLE_ROWS, /* frame height */
+ bgx /* fill color */
+ );
+#else
+ memsetl(CONSOLE_ROW_FIRST, CONSOLE_SIZE, bgx);
+#endif
+}
+
+static void console_cursor_fix(void)
+{
+ if (console_row < 0)
+ console_row = 0;
+ if (console_row >= CONSOLE_ROWS)
+ console_row = CONSOLE_ROWS - 1;
+ if (console_col < 0)
+ console_col = 0;
+ if (console_col >= CONSOLE_COLS)
+ console_col = CONSOLE_COLS - 1;
+}
+
+static void console_cursor_up(int n)
+{
+ console_row -= n;
+ console_cursor_fix();
+}
+
+static void console_cursor_down(int n)
+{
+ console_row += n;
+ console_cursor_fix();
+}
+
+static void console_cursor_left(int n)
+{
+ console_col -= n;
+ console_cursor_fix();
+}
+
+static void console_cursor_right(int n)
+{
+ console_col += n;
+ console_cursor_fix();
+}
+
+static void console_cursor_set_position(int row, int col)
+{
+ if (console_row != -1)
+ console_row = row;
+ if (console_col != -1)
+ console_col = col;
+ console_cursor_fix();
+}
+
+static void console_previousline(int n)
{
- console_row++;
+ /* FIXME: also scroll terminal ? */
+ console_row -= n;
+ console_cursor_fix();
+}
+
+static void console_swap_colors(void)
+{
+ eorx = fgx;
+ fgx = bgx;
+ bgx = eorx;
+ eorx = fgx ^ bgx;
+}
+
+static inline int console_cursor_is_visible(void)
+{
+ return !ansi_cursor_hidden;
+}
+#else
+static inline int console_cursor_is_visible(void)
+{
+ return 1;
+}
+#endif
+
+static void console_newline(int n)
+{
+ console_row += n;
console_col = 0;
/* Check if we need to scroll the terminal */
@@ -779,7 +874,7 @@ static void console_newline(void)
console_scrollup();
/* Decrement row number */
- console_row--;
+ console_row = CONSOLE_ROWS - 1;
}
}
@@ -788,11 +883,12 @@ static void console_cr(void)
console_col = 0;
}
-void video_putc(const char c)
+static void parse_putc(const char c)
{
static int nl = 1;
- CURSOR_OFF;
+ if (console_cursor_is_visible())
+ CURSOR_OFF;
switch (c) {
case 13: /* back to first column */
@@ -801,7 +897,7 @@ void video_putc(const char c)
case '\n': /* next line */
if (console_col || (!console_col && nl))
- console_newline();
+ console_newline(1);
nl = 1;
break;
@@ -810,7 +906,7 @@ void video_putc(const char c)
console_col &= ~0x0007;
if (console_col >= CONSOLE_COLS)
- console_newline();
+ console_newline(1);
break;
case 8: /* backspace */
@@ -827,11 +923,225 @@ void video_putc(const char c)
/* check for newline */
if (console_col >= CONSOLE_COLS) {
- console_newline();
+ console_newline(1);
nl = 0;
}
}
- CURSOR_SET;
+
+ if (console_cursor_is_visible())
+ CURSOR_SET;
+}
+
+void video_putc(const char c)
+{
+#ifdef CONFIG_CFB_CONSOLE_ANSI
+ int i;
+
+ if (c == 27) {
+ for (i = 0; i < ansi_buf_size; ++i)
+ parse_putc(ansi_buf[i]);
+ ansi_buf[0] = 27;
+ ansi_buf_size = 1;
+ return;
+ }
+
+ if (ansi_buf_size > 0) {
+ /*
+ * 0 - ESC
+ * 1 - [
+ * 2 - num1
+ * 3 - ..
+ * 4 - ;
+ * 5 - num2
+ * 6 - ..
+ * - cchar
+ */
+ int next = 0;
+
+ int flush = 0;
+ int fail = 0;
+
+ int num1 = 0;
+ int num2 = 0;
+ int cchar = 0;
+
+ ansi_buf[ansi_buf_size++] = c;
+
+ if (ansi_buf_size >= sizeof(ansi_buf))
+ fail = 1;
+
+ for (i = 0; i < ansi_buf_size; ++i) {
+ if (fail)
+ break;
+
+ switch (next) {
+ case 0:
+ if (ansi_buf[i] == 27)
+ next = 1;
+ else
+ fail = 1;
+ break;
+
+ case 1:
+ if (ansi_buf[i] == '[')
+ next = 2;
+ else
+ fail = 1;
+ break;
+
+ case 2:
+ if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') {
+ num1 = ansi_buf[i]-'0';
+ next = 3;
+ } else if (ansi_buf[i] != '?') {
+ --i;
+ num1 = 1;
+ next = 4;
+ }
+ break;
+
+ case 3:
+ if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') {
+ num1 *= 10;
+ num1 += ansi_buf[i]-'0';
+ } else {
+ --i;
+ next = 4;
+ }
+ break;
+
+ case 4:
+ if (ansi_buf[i] != ';') {
+ --i;
+ next = 7;
+ } else
+ next = 5;
+ break;
+
+ case 5:
+ if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') {
+ num2 = ansi_buf[i]-'0';
+ next = 6;
+ } else
+ fail = 1;
+ break;
+
+ case 6:
+ if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') {
+ num2 *= 10;
+ num2 += ansi_buf[i]-'0';
+ } else {
+ --i;
+ next = 7;
+ }
+ break;
+
+ case 7:
+ if ((ansi_buf[i] >= 'A' && ansi_buf[i] <= 'H')
+ || ansi_buf[i] == 'J'
+ || ansi_buf[i] == 'K'
+ || ansi_buf[i] == 'h'
+ || ansi_buf[i] == 'l'
+ || ansi_buf[i] == 'm') {
+ cchar = ansi_buf[i];
+ flush = 1;
+ } else
+ fail = 1;
+ break;
+ }
+ }
+
+ if (fail) {
+ for (i = 0; i < ansi_buf_size; ++i)
+ parse_putc(ansi_buf[i]);
+ ansi_buf_size = 0;
+ return;
+ }
+
+ if (flush) {
+ if (!ansi_cursor_hidden)
+ CURSOR_OFF;
+ ansi_buf_size = 0;
+ switch (cchar) {
+ case 'A':
+ /* move cursor num1 rows up */
+ console_cursor_up(num1);
+ break;
+ case 'B':
+ /* move cursor num1 rows down */
+ console_cursor_down(num1);
+ break;
+ case 'C':
+ /* move cursor num1 columns forward */
+ console_cursor_right(num1);
+ break;
+ case 'D':
+ /* move cursor num1 columns back */
+ console_cursor_left(num1);
+ break;
+ case 'E':
+ /* move cursor num1 rows up at begin of row */
+ console_previousline(num1);
+ break;
+ case 'F':
+ /* move cursor num1 rows down at begin of row */
+ console_newline(num1);
+ break;
+ case 'G':
+ /* move cursor to column num1 */
+ console_cursor_set_position(-1, num1-1);
+ break;
+ case 'H':
+ /* move cursor to row num1, column num2 */
+ console_cursor_set_position(num1-1, num2-1);
+ break;
+ case 'J':
+ /* clear console and move cursor to 0, 0 */
+ console_clear();
+ console_cursor_set_position(0, 0);
+ break;
+ case 'K':
+ /* clear line */
+ if (num1 == 0)
+ console_clear_line(console_row,
+ console_col,
+ CONSOLE_COLS-1);
+ else if (num1 == 1)
+ console_clear_line(console_row,
+ 0, console_col);
+ else
+ console_clear_line(console_row,
+ 0, CONSOLE_COLS-1);
+ break;
+ case 'h':
+ ansi_cursor_hidden = 0;
+ break;
+ case 'l':
+ ansi_cursor_hidden = 1;
+ break;
+ case 'm':
+ if (num1 == 0) { /* reset swapped colors */
+ if (ansi_colors_need_revert) {
+ console_swap_colors();
+ ansi_colors_need_revert = 0;
+ }
+ } else if (num1 == 7) { /* once swap colors */
+ if (!ansi_colors_need_revert) {
+ console_swap_colors();
+ ansi_colors_need_revert = 1;
+ }
+ }
+ break;
+ }
+ if (!ansi_cursor_hidden)
+ CURSOR_SET;
+ }
+ } else {
+ parse_putc(c);
+ }
+#else
+ parse_putc(c);
+#endif
}
void video_puts(const char *s)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 58d62d0c7d..cdb6697890 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -158,9 +158,15 @@
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* I2C Configuration */
#define CONFIG_I2C
@@ -182,11 +188,7 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1 1
-#define CONFIG_CONS_INDEX 1
+#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_ENV_IS_NOWHERE
diff --git a/include/configs/eco5pk.h b/include/configs/eco5pk.h
new file mode 100644
index 0000000000..b9ebf6a2a8
--- /dev/null
+++ b/include/configs/eco5pk.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2012 8D Technologies inc.
+ * Based on mt_ventoux.h, original banner below:
+ *
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2009 TechNexion Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tam3517-common.h"
+
+#undef CONFIG_USB_EHCI
+#undef CONFIG_USB_EHCI_OMAP
+#undef CONFIG_USB_OMAP3
+#undef CONFIG_CMD_USB
+
+/* Our console port is port3 */
+#undef CONFIG_CONS_INDEX
+#undef CONFIG_SYS_NS16550_COM1
+#undef CONFIG_SERIAL1
+
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3
+
+#define MACH_TYPE_ECO5_PK 4017
+#define CONFIG_MACH_TYPE MACH_TYPE_ECO5_PK
+
+#define CONFIG_BOOTDELAY 10
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT "ECO5-PK # "
+#define CONFIG_SYS_PROMPT V_PROMPT
+
+/*
+ * Set its own mtdparts, different from common
+ */
+#undef MTDIDS_DEFAULT
+#undef MTDPARTS_DEFAULT
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(xloader-nand)," \
+ "1024k(uboot-nand),256k(params-nand)," \
+ "5120k(kernel),-(ubifs)"
+
+/*
+ * The arithmetic in tam3517.h is wrong for us and the kernel gets overwritten.
+ */
+#undef CONFIG_ENV_OFFSET_REDUND
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_SYS_ENV_SECT_SIZE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
+ "install_kernel=if dhcp $bootfile; then nand erase kernel;" \
+ "nand write $fileaddr kernel; fi\0" \
+ "mtdparts="MTDPARTS_DEFAULT"\0" \
+ "serverip=192.168.142.60\0"
+
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
new file mode 100644
index 0000000000..8506604a76
--- /dev/null
+++ b/include/configs/nokia_rx51.h
@@ -0,0 +1,452 @@
+/*
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2010
+ * Alistair Buxton <a.j.buxton@gmail.com>
+ *
+ * Derived from Beagle Board code:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the Nokia RX-51 aka N900.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_OMAP34XX /* which is a 34XX */
+#define CONFIG_OMAP3430 /* which is in a 3430 */
+#define CONFIG_OMAP3_RX51 /* working with RX51 */
+#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
+
+#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51
+
+/*
+ * Nokia X-Loader loading secondary image to address 0x80400000
+ * NOLO loading boot image to random place, so it doesn't really
+ * matter what we set this to. We have to copy u-boot to this address
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+#include <asm/arch/mem.h>
+#include <linux/stringify.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */
+
+#define CONFIG_CMDLINE_TAG /* enable passing kernel command line string */
+#define CONFIG_INITRD_TAG /* enable passing initrd */
+#define CONFIG_REVISION_TAG /* enable passing revision tag*/
+#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_UBI_SIZE (512 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \
+ (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 on RX-51 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_MUSB_UDC
+#define CONFIG_MUSB_HDC
+#define CONFIG_USB_OMAP3
+#define CONFIG_TWL4030_USB
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USBD_VENDORID 0x0421
+#define CONFIG_USBD_PRODUCTID 0x01c8
+#define CONFIG_USBD_MANUFACTURER "Nokia"
+#define CONFIG_USBD_PRODUCT_NAME "N900"
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_NO_FLASH
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_EXT4 /* EXT4 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_GPIO /* Enable gpio command */
+
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+
+#define CONFIG_CMD_CLEAR /* ANSI terminal clear screen command */
+
+#ifdef ONENAND_SUPPORT
+
+#define CONFIG_CMD_ONENAND /* ONENAND support */
+#define CONFIG_CMD_MTDPARTS /* mtd parts support */
+
+#ifdef UBIFS_SUPPORT
+#define CONFIG_CMD_UBI /* UBI Support */
+#define CONFIG_CMD_UBIFS /* UBIFS Support */
+#endif
+
+#endif
+
+/* commands not needed from config_cmd_default.h */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#undef CONFIG_CMD_NFS /* NFS support */
+#undef CONFIG_CMD_SAVEENV /* saveenv */
+#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+
+#define CONFIG_OMAP3_SPI
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_DRIVER_OMAP34XX_I2C
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+#define CONFIG_TWL4030_LED
+#define CONFIG_TWL4030_KEYPAD
+
+#define CONFIG_OMAP_GPIO
+#define GPIO_SLIDE 71
+
+/*
+ * Board ONENAND Info.
+ */
+
+#define PART1_NAME "bootloader"
+#define PART1_SIZE 128
+#define PART1_MULL 1024
+#define PART1_SUFF "k"
+#define PART1_OFFS 0x00000000
+#define PART1_MASK 0x00000003
+
+#define PART2_NAME "config"
+#define PART2_SIZE 384
+#define PART2_MULL 1024
+#define PART2_SUFF "k"
+#define PART2_OFFS 0x00020000
+#define PART2_MASK 0x00000000
+
+#define PART3_NAME "log"
+#define PART3_SIZE 256
+#define PART3_MULL 1024
+#define PART3_SUFF "k"
+#define PART3_OFFS 0x00080000
+#define PART3_MASK 0x00000000
+
+#define PART4_NAME "kernel"
+#define PART4_SIZE 2
+#define PART4_MULL 1024*1024
+#define PART4_SUFF "m"
+#define PART4_OFFS 0x000c0000
+#define PART4_MASK 0x00000000
+
+#define PART5_NAME "initfs"
+#define PART5_SIZE 2
+#define PART5_MULL 1024*1024
+#define PART5_SUFF "m"
+#define PART5_OFFS 0x002c0000
+#define PART5_MASK 0x00000000
+
+#define PART6_NAME "rootfs"
+#define PART6_SIZE 257280
+#define PART6_MULL 1024
+#define PART6_SUFF "k"
+#define PART6_OFFS 0x004c0000
+#define PART6_MASK 0x00000000
+
+#ifdef ONENAND_SUPPORT
+
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#ifdef UBIFS_SUPPORT
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#endif
+
+#define MTDIDS_DEFAULT "onenand0=onenand"
+#define MTDPARTS_DEFAULT "mtdparts=onenand:" \
+ __stringify(PART1_SIZE) PART1_SUFF "(" PART1_NAME ")ro," \
+ __stringify(PART2_SIZE) PART2_SUFF "(" PART2_NAME ")," \
+ __stringify(PART3_SIZE) PART3_SUFF "(" PART3_NAME ")," \
+ __stringify(PART4_SIZE) PART4_SUFF "(" PART4_NAME ")," \
+ __stringify(PART5_SIZE) PART5_SUFF "(" PART5_NAME ")," \
+ "-(" PART6_NAME ")"
+
+#endif
+
+/* Watchdog support */
+#define CONFIG_HW_WATCHDOG
+
+/*
+ * Framebuffer
+ */
+/* Video console */
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_CFB_CONSOLE_ANSI /* Enable ANSI escape codes in framebuffer */
+#define CONFIG_VIDEO_LOGO
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+
+/* functions for cfb_console */
+#define VIDEO_KBD_INIT_FCT rx51_kp_init()
+#define VIDEO_TSTC_FCT rx51_kp_tstc
+#define VIDEO_GETC_FCT rx51_kp_getc
+#ifndef __ASSEMBLY__
+int rx51_kp_init(void);
+int rx51_kp_tstc(void);
+int rx51_kp_getc(void);
+#endif
+
+#ifndef MTDPARTS_DEFAULT
+#define MTDPARTS_DEFAULT
+#endif
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "usbtty=cdc_acm\0" \
+ "stdin=vga\0" \
+ "stdout=vga\0" \
+ "stderr=vga\0" \
+ "setcon=setenv stdin ${con};" \
+ "setenv stdout ${con};" \
+ "setenv stderr ${con}\0" \
+ "sercon=setenv con serial; run setcon\0" \
+ "usbcon=setenv con usbtty; run setcon\0" \
+ "vgacon=setenv con vga; run setcon\0" \
+ "slide=gpio input " __stringify(GPIO_SLIDE) "\0" \
+ "switchmmc=mmc dev ${mmcnum}\0" \
+ "kernaddr=0x82008000\0" \
+ "initrdaddr=0x84008000\0" \
+ "scriptaddr=0x86008000\0" \
+ "fileload=${mmctype}load mmc ${mmcnum}:${mmcpart} " \
+ "${loadaddr} ${mmcfile}\0" \
+ "kernload=setenv loadaddr ${kernaddr};" \
+ "setenv mmcfile ${mmckernfile};" \
+ "run fileload\0" \
+ "initrdload=setenv loadaddr ${initrdaddr};" \
+ "setenv mmcfile ${mmcinitrdfile};" \
+ "run fileload\0" \
+ "scriptload=setenv loadaddr ${scriptaddr};" \
+ "setenv mmcfile ${mmcscriptfile};" \
+ "run fileload\0" \
+ "scriptboot=echo Running ${mmcscriptfile} from mmc " \
+ "${mmcnum}:${mmcpart} ...; source ${scriptaddr}\0" \
+ "kernboot=echo Booting ${mmckernfile} from mmc " \
+ "${mmcnum}:${mmcpart} ...; bootm ${kernaddr}\0" \
+ "kerninitrdboot=echo Booting ${mmckernfile} ${mmcinitrdfile} from mmc "\
+ "${mmcnum}:${mmcpart} ...; bootm ${kernaddr} ${initrdaddr}\0" \
+ "attachboot=echo Booting attached kernel image ...;" \
+ "setenv setup_omap_atag 1;" \
+ "bootm ${attkernaddr};" \
+ "setenv setup_omap_atag\0" \
+ "trymmcscriptboot=if run switchmmc; then " \
+ "if run scriptload; then " \
+ "run scriptboot;" \
+ "fi;" \
+ "fi\0" \
+ "trymmckernboot=if run switchmmc; then " \
+ "if run kernload; then " \
+ "run kernboot;" \
+ "fi;" \
+ "fi\0" \
+ "trymmckerninitrdboot=if run switchmmc; then " \
+ "if run initrdload; then " \
+ "if run kernload; then " \
+ "run kerninitrdboot;" \
+ "fi;" \
+ "fi; " \
+ "fi\0" \
+ "trymmcpartboot=setenv mmcscriptfile boot.scr; run trymmcscriptboot;" \
+ "setenv mmckernfile uImage; run trymmckernboot\0" \
+ "trymmcallpartboot=setenv mmcpart 1; run trymmcpartboot;" \
+ "setenv mmcpart 2; run trymmcpartboot;" \
+ "setenv mmcpart 3; run trymmcpartboot;" \
+ "setenv mmcpart 4; run trymmcpartboot\0" \
+ "trymmcboot=if run switchmmc; then " \
+ "setenv mmctype fat;" \
+ "run trymmcallpartboot;" \
+ "setenv mmctype ext2;" \
+ "run trymmcallpartboot;" \
+ "setenv mmctype ext4;" \
+ "run trymmcallpartboot;" \
+ "fi\0" \
+ "emmcboot=setenv mmcnum 1; run trymmcboot\0" \
+ "sdboot=setenv mmcnum 0; run trymmcboot\0" \
+ ""
+
+#define CONFIG_PREBOOT \
+ "if run slide; then true; else run attachboot; fi;" \
+ "echo Extra commands:;" \
+ "echo run sercon - Use serial port for control.;" \
+ "echo run usbcon - Use usbtty for control.;" \
+ "echo run vgacon - Use framebuffer/keyboard.;" \
+ "echo run sdboot - Boot from SD card slot.;" \
+ "echo run emmcboot - Boot internal eMMC memory.;" \
+ "echo run attachboot - Boot attached kernel image.;" \
+ "echo"
+
+#define CONFIG_BOOTCOMMAND \
+ "run sdboot;" \
+ "run emmcboot;" \
+ "run attachboot;" \
+ "echo"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "Nokia RX-51 # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)/*31MB*/
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Attached kernel image
+ */
+
+#define SDRAM_SIZE 0x10000000 /* 256 MB */
+#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE)
+
+#define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */
+#define KERNEL_OFFSET 0x40000 /* 256 kB */
+#define KERNEL_MAXSIZE (IMAGE_MAXSIZE-KERNEL_OFFSET)
+#define KERNEL_ADDRESS (SDRAM_END-KERNEL_MAXSIZE)
+
+/* Reserve protected RAM for attached kernel */
+#define CONFIG_PRAM ((KERNEL_MAXSIZE >> 10)+1)
+
+#endif /* __CONFIG_H */
diff --git a/include/twl4030.h b/include/twl4030.h
index 9cd32ab45a..0c17f5929b 100644
--- a/include/twl4030.h
+++ b/include/twl4030.h
@@ -151,6 +151,103 @@
#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1)
#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
+/* Power bus message definitions */
+
+/* The TWL4030/5030 splits its power-management resources (the various
+ * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
+ * P3. These groups can then be configured to transition between sleep, wait-on
+ * and active states by sending messages to the power bus. See Section 5.4.2
+ * Power Resources of TWL4030 TRM
+ */
+
+/* Processor groups */
+#define DEV_GRP_NULL 0x0
+#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
+#define DEV_GRP_P2 0x2 /* P2: all Modem devices */
+#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
+
+/* Resource groups */
+#define RES_GRP_RES 0x0 /* Reserved */
+#define RES_GRP_PP 0x1 /* Power providers */
+#define RES_GRP_RC 0x2 /* Reset and control */
+#define RES_GRP_PP_RC 0x3
+#define RES_GRP_PR 0x4 /* Power references */
+#define RES_GRP_PP_PR 0x5
+#define RES_GRP_RC_PR 0x6
+#define RES_GRP_ALL 0x7 /* All resource groups */
+
+#define RES_TYPE2_R0 0x0
+
+#define RES_TYPE_ALL 0x7
+
+/* Resource states */
+#define RES_STATE_WRST 0xF
+#define RES_STATE_ACTIVE 0xE
+#define RES_STATE_SLEEP 0x8
+#define RES_STATE_OFF 0x0
+
+/* Power resources */
+
+/* Power providers */
+#define RES_VAUX1 1
+#define RES_VAUX2 2
+#define RES_VAUX3 3
+#define RES_VAUX4 4
+#define RES_VMMC1 5
+#define RES_VMMC2 6
+#define RES_VPLL1 7
+#define RES_VPLL2 8
+#define RES_VSIM 9
+#define RES_VDAC 10
+#define RES_VINTANA1 11
+#define RES_VINTANA2 12
+#define RES_VINTDIG 13
+#define RES_VIO 14
+#define RES_VDD1 15
+#define RES_VDD2 16
+#define RES_VUSB_1V5 17
+#define RES_VUSB_1V8 18
+#define RES_VUSB_3V1 19
+#define RES_VUSBCP 20
+#define RES_REGEN 21
+/* Reset and control */
+#define RES_NRES_PWRON 22
+#define RES_CLKEN 23
+#define RES_SYSEN 24
+#define RES_HFCLKOUT 25
+#define RES_32KCLKOUT 26
+#define RES_RESET 27
+/* Power Reference */
+#define RES_Main_Ref 28
+
+#define TOTAL_RESOURCES 28
+/*
+ * Power Bus Message Format ... these can be sent individually by Linux,
+ * but are usually part of downloaded scripts that are run when various
+ * power events are triggered.
+ *
+ * Broadcast Message (16 Bits):
+ * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
+ * RES_STATE[3:0]
+ *
+ * Singular Message (16 Bits):
+ * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
+ */
+
+#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
+ ((devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
+ | (type) << 4 | (state))
+
+#define MSG_SINGULAR(devgrp, id, state) \
+ ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
+
+#define MSG_BROADCAST_ALL(devgrp, state) \
+ ((devgrp) << 5 | (state))
+
+#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
+#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
+#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
+
/* Power Managment Receiver */
#define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B
#define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C
@@ -311,6 +408,7 @@
#define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03
#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02
#define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03
+#define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03
/* Device Selection in PM Receiver Module */
#define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 15:02:14 +0000