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authorPalmer Dabbelt <palmer@sifive.com>2017-11-28 14:04:05 -0800
committerPalmer Dabbelt <palmer@sifive.com>2017-11-28 14:04:05 -0800
commit9347ce54cd699db92d37e66191aa4b9a0a92304e (patch)
treec33fd1368232b09cb0aaf72593766ebdc8e1b0dd /arch/riscv
parent3343eb6806f365b9e3d451040671fa9336e57513 (diff)
RISC-V: __test_and_op_bit_ord should be strongly ordered
I mis-read the documentation. After looking at it again the documentation is actually as clear as it can be, it's just that I didn't actually read it in order and therefor did the wrong thing. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/include/asm/bitops.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h
index 7c281ef1d583..f30daf26f08f 100644
--- a/arch/riscv/include/asm/bitops.h
+++ b/arch/riscv/include/asm/bitops.h
@@ -67,7 +67,7 @@
: "memory");
#define __test_and_op_bit(op, mod, nr, addr) \
- __test_and_op_bit_ord(op, mod, nr, addr, )
+ __test_and_op_bit_ord(op, mod, nr, addr, .aqrl)
#define __op_bit(op, mod, nr, addr) \
__op_bit_ord(op, mod, nr, addr, )