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AgeCommit message (Expand)Author
2020-05-11rs6000: Vector string isolate instructionsKelvin Nilsen
2020-05-11rs6000: Add xxeval and vec_ternarylogicKelvin Nilsen
2020-05-11rs6000: Add pdepd and pextdKelvin Nilsen
2020-05-11rs6000: Add vclrlb and vclrrbKelvin Nilsen
2020-05-11rs6000: Add cntlzdm and cnttzdmKelvin Nilsen
2020-05-11i386: Add V2SFmode sqrt insn pattern [PR95046]Uros Bizjak
2020-05-11rs6000: Add vcfuged instructionKelvin Nilsen
2020-05-11rs6000: Add scalar cfuged instructionKelvin Nilsen
2020-05-11rs6000: Add vgnbKelvin Nilsen
2020-05-11rs6000: Add vector pdep/pextKelvin Nilsen
2020-05-11rs6000: Add vector count under maskKelvin Nilsen
2020-05-11i386: Improve basic vectorized V2SFmode operations [PR95046]Uros Bizjak
2020-05-11aarch64: Fix ICE when expanding scalar floating move with -mgeneral-regs-only...Fei Yang
2020-05-11[PATCH] aarch64: prefer using csinv, csneg in zero extend contextsAlex Coplan
2020-05-11i386: Vectorize basic V2SFmode operations [PR94913]Uros Bizjak
2020-05-10i386: Define __ILP32__ and _ILP32 for all 32-bit targetsGerald Pfeifer
2020-05-09cris: Enable "neg" to set condition codes.Hans-Peter Nilsson
2020-05-09cris: Enable single-bit btst/btstq to set condition codes.Hans-Peter Nilsson
2020-05-09cris: Enable 32-bit shifts, clz, bswap, umin to set condition codes.Hans-Peter Nilsson
2020-05-09cris: Enable general "and", "or", "xor", "not" to set condition codes.Hans-Peter Nilsson
2020-05-09cris: Enable additions and subtractions to set condition codes.Hans-Peter Nilsson
2020-05-09cris: Enable extend operations to SImode to set condition codes.Hans-Peter Nilsson
2020-05-09cris: Enable movhi and movqi to set condition codes. Anonymize.Hans-Peter Nilsson
2020-05-09cris: Enable *movsi_internal to set condition codes.Hans-Peter Nilsson
2020-05-09cris: Introduce CC_NZVCmode and CC_NZmode.Hans-Peter Nilsson
2020-05-09cris.md: Post-reload, split/generate clobberless zero source movesHans-Peter Nilsson
2020-05-09cris.md: Post-reload, split/generate clobberless memory destination movesHans-Peter Nilsson
2020-05-09config/cris/cris.h (REVERSIBLE_CC_MODE): Define to true.Hans-Peter Nilsson
2020-05-09cris: Define TARGET_FLAGS_REGNUM.Hans-Peter Nilsson
2020-05-09cris: Emit trivial btstq expected by gcc.target/cris/sync-2i.c, sync-2c.cHans-Peter Nilsson
2020-05-09cris: Move trivially from cc0 to reg:CC model, removing most optimizations.Hans-Peter Nilsson
2020-05-09gcc/config/cris: Remove shared-library and CRIS v32 support.Hans-Peter Nilsson
2020-05-09gcc/config/cris/t-elfmulti: Remove crisv32 multilib.Hans-Peter Nilsson
2020-05-09cris: Remove from gcc/config/cris: t-linux, linux.h, linux.optHans-Peter Nilsson
2020-05-08ix86: Add peephole2 for *add<mode>3_cc_overflow_1 followed by matching memory...Jakub Jelinek
2020-05-07rs6000: New insns setnbc and setnbcrSegher Boessenkool
2020-05-07rs6000: New insns setbc and setbcrSegher Boessenkool
2020-05-07Move all patterns and expanders out of h8300.md and into other files that are...Jeff Law
2020-05-07 More cleanups. Merging patterns with iterators, split out peepholes, etc.Jeff Law
2020-05-07 Drop original H8/300 support. This should generate identical code for th...Jeff Law
2020-05-07Drop more COFF support from H8 portJeff Law
2020-05-07Remove remnants of COFF support which was dropped eons ago.Jeff Law
2020-05-07AArch32: fix bootstrap failureAlex Coplan
2020-05-07alpha: Implement the PR94780 fix for alpha.Uros Bizjak
2020-05-06x86: Fix vextract* masked patterns [PR93069]Jakub Jelinek
2020-05-06i386: Use ADD to implement compares with negated operand [PR94913]Uros Bizjak
2020-05-06aarch64: fix conflicting declarationsAndreas Schwab
2020-05-06Enable TARGET_TSXLDTRK for GCC support.liuhongt
2020-05-06riscv: Fix up riscv_atomic_assign_expand_fenv [PR94950]Jakub Jelinek
2020-05-06Enable GCC support for SERIALIZEliuhongt
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