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AgeCommit message (Expand)Author
2020-03-19[rs6000] Rewrite the declaration of a variableBin Bin Lv
2020-03-18rs6000: Add back some w* constraints (PR91886)Segher Boessenkool
2020-03-17Fix up duplicated duplicated words mostly in commentsJakub Jelinek
2020-03-13Fix UBSAN error, shifting 64 bit value by 64.Aaron Sawdey
2020-03-11[rs6000] Fix a wrong GC issueBin Bin Lv
2020-03-11rs6000: Check -+0 and NaN for smax/smin generationJiufu Guo
2020-03-10PR90763: PowerPC vec_xl_len should take const argument.Will Schmidt
2020-03-09rs6000: Fix -mlong-double documentationCarl Love
2020-03-09Restore alignment in rs6000 target.Martin Liska
2020-03-06rs6000: Correct logic to disable NO_SUM_IN_TOC and NO_FP_IN_TOC [PR94065]David Edelsohn
2020-03-04rs6000: Fix -mpower9-vector -mno-altivec ICE (PR87560)Bill Schmidt
2020-02-28Fix target/93937Michael Meissner
2020-02-27Fix PR target/93932Michael Meissner
2020-02-20rs6000: Fix infinite loop building ghostscript and icu [PR93658]Peter Bergner
2020-02-17Fix double quoting.Martin Liska
2020-02-17rs6000: mark clobber for registers changed by untpyed_callJiufu Guo
2020-02-12rs6000: Use strlen instead of sizeof - 1Segher Boessenkool
2020-02-11Rename -mprefixed-addr to be -mprefixed, and document it.Michael Meissner
2020-02-07powerpc: Fix -fstack-clash-protection -mprefixed-addr ICE [PR93122]Jakub Jelinek
2020-02-06Fix PR 93569.Michael Meissner
2020-02-06rs6000: Use rldimi for 64-bit constants with high=low (PR93012)Segher Boessenkool
2020-02-05Fix PR 93568 (thinko)Michael Meissner
2020-02-03Optimize vec_extract of vectors in memory with a PC-relative address.Michael Meissner
2020-02-03Rewrite convulated code to avoid adding r0.Michael Meissner
2020-02-03Adjust how variable vector extraction is done.Michael Meissner
2020-02-03Add some gcc_asserts for vector extract processing.Michael Meissner
2020-02-03rs6000: Update constraint documentationSegher Boessenkool
2020-01-21Remove dead variable.Martin Liska
2020-01-21powerpc: Fix ICE with fp conditional move (PR target/93073)Jakub Jelinek
2020-01-07Revert patch accidentily created on the wrong sandboxMichael Meissner
2020-01-07Restore patch reverted on trunk instead of a branchMichael Meissner
2020-01-07Refactor some code for a future change.Michael Meissner
2020-01-07Update 'Q' constraint documentation.Michael Meissner
2020-01-07Fix bad code of vector extract of PC-relative address with variable element #.Michael Meissner
2020-01-07Add support for large prefixed address in adjusting a vector address.Michael Meissner
2020-01-01Update copyright years.Jakub Jelinek
2019-12-30Define STARTFILE_PREFIX_SPEC for powerpc VxWorks < 7Doug Rupp
2019-12-30Fix builtin functions needlessly using VIEW_CONVERT_EXPRs on their operands.Peter Bergner
2019-12-24rs6000: re-enable web and rnreg with -funroll-loopsJiufu Guo
2019-12-20Rename signed integer 16/34-bit macros.Michael Meissner
2019-12-17Generate PADDI to add large constants if -mcpu=future.Michael Meissner
2019-12-17Use PLI to load up 32-bit SImode constants if -mcpu=future.Michael Meissner
2019-12-17Use PLI to load up large constants if -mcpu=future.Michael Meissner
2019-12-16rs6000: Use symbolic names for the CR fields in more casesSegher Boessenkool
2019-12-14[Darwin, PPC] Use Darwin9 bundle header for Rosetta builds.Iain Sandoe
2019-12-13[Darwin, PPC] Use Darwin9 dylib header for Rosetta builds.Iain Sandoe
2019-12-13[rs6000] Adjust vectorization cost for scalar COND_EXPRKewen Lin
2019-12-09rs6000: Name set<mode>_cc, and delete some old mfcr patternsSegher Boessenkool
2019-12-04Do not define builtins that overload disabled builtins.Peter Bergner
2019-12-04[rs6000] Fix PR92760 by checking VECTOR_MEM_NONE_P insteadKewen Lin
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