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authorUros Bizjak <uros@gcc.gnu.org>2014-01-05 16:42:07 +0100
committerUros Bizjak <uros@gcc.gnu.org>2014-01-05 16:42:07 +0100
commitc30f016cf5e87690eed163a330f8c6ae9598e3e9 (patch)
tree07c56f0d0a03356895ebb36f8e012ac769cd0aac /gcc
parent18a68db933cafeea6c261235608de627216e45a3 (diff)
i386.c (ix86_data_alignment): Calculate max_align from prefetch_block tune setting.
* config/i386/i386.c (ix86_data_alignment): Calculate max_align from prefetch_block tune setting. (nocona_cost): Correct size of prefetch block to 64. From-SVN: r206345
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog27
-rw-r--r--gcc/ChangeLog-201355
-rw-r--r--gcc/config/i386/i386.c14
3 files changed, 54 insertions, 42 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 83b39e24650..600c24bed73 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2014-01-05 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.c (ix86_data_alignment): Calculate max_align
+ from prefetch_block tune setting.
+ (nocona_cost): Correct size of prefetch block to 64.
+
2014-01-04 Eric Botcazou <ebotcazou@adacore.com>
* config/arm/arm.c (arm_get_frame_offsets): Revamp long lines.
@@ -24,7 +30,7 @@
2014-01-03 Bingfeng Mei <bmei@broadcom.com>
PR tree-optimization/59651
- * tree-vect-loop-manip.c (vect_create_cond_for_alias_checks):
+ * tree-vect-loop-manip.c (vect_create_cond_for_alias_checks):
Address range for negative step should be added by TYPE_SIZE_UNIT.
2014-01-03 Andreas Schwab <schwab@linux-m68k.org>
@@ -102,20 +108,21 @@
2014-01-02 Richard Sandiford <rdsandiford@googlemail.com>
- Update copyright years
+ Update copyright years.
2014-01-02 Richard Sandiford <rdsandiford@googlemail.com>
* common/config/arc/arc-common.c, config/arc/arc-modes.def,
config/arc/arc-protos.h, config/arc/arc.c, config/arc/arc.h,
- config/arc/arc.md, config/arc/arc.opt, config/arm/arm_neon_builtins.def,
- config/arm/crypto.def, config/i386/avx512cdintrin.h,
- config/i386/avx512erintrin.h, config/i386/avx512fintrin.h,
- config/i386/avx512pfintrin.h, config/i386/btver2.md,
- config/i386/shaintrin.h, config/i386/slm.md, config/linux-protos.h,
- config/linux.c, config/winnt-c.c, diagnostic-color.c,
- diagnostic-color.h, gimple-ssa-isolate-paths.c, vtable-verify.c,
- vtable-verify.h: Use the standard form for the copyright notice.
+ config/arc/arc.md, config/arc/arc.opt,
+ config/arm/arm_neon_builtins.def, config/arm/crypto.def,
+ config/i386/avx512cdintrin.h, config/i386/avx512erintrin.h,
+ config/i386/avx512fintrin.h, config/i386/avx512pfintrin.h,
+ config/i386/btver2.md, config/i386/shaintrin.h, config/i386/slm.md,
+ config/linux-protos.h, config/linux.c, config/winnt-c.c,
+ diagnostic-color.c, diagnostic-color.h, gimple-ssa-isolate-paths.c,
+ vtable-verify.c, vtable-verify.h: Use the standard form for the
+ copyright notice.
2014-01-02 Tobias Burnus <burnus@net-b.de>
diff --git a/gcc/ChangeLog-2013 b/gcc/ChangeLog-2013
index 2ffd9593b54..2c11878a134 100644
--- a/gcc/ChangeLog-2013
+++ b/gcc/ChangeLog-2013
@@ -62,19 +62,19 @@
(_mm_roundscale_ss): Ditto.
(_mm_roundscale_sd): Ditto.
* config/i386/i386-builtin-types.def: New types to support
- new built-ins: <V2DF, V2DF, V2DF, INT, INT>, <V4SF, V4SF, V4SF, INT, INT>,
- <(V4SF, V4SF, V2DF, INT>, <V2DF, V2DF, V4SF, INT>,
- <V4SF, V4SF, V4SF, V4SF, IN>.
- * config/i386/i386.c (enum ix86_builtins): Add IX86_BUILTIN_ADDSD_ROUND,
- IX86_BUILTIN_ADDSS_ROUND, IX86_BUILTIN_CVTSD2SS_ROUND,
- IX86_BUILTIN_CVTSS2SD_ROUND, IX86_BUILTIN_DIVSD_ROUND,
- IX86_BUILTIN_GETEXPSD128, IX86_BUILTIN_DIVSS_ROUND,
- IX86_BUILTIN_GETEXPSS128, IX86_BUILTIN_GETMANTSD128,
- IX86_BUILTIN_GETMANTSS128, IX86_BUILTIN_MAXSD_ROUND,
- IX86_BUILTIN_MAXSS_ROUND, IX86_BUILTIN_MINSD_ROUND,
- IX86_BUILTIN_MINSS_ROUND, IX86_BUILTIN_MULSD_ROUND,
- IX86_BUILTIN_MULSS_ROUND, IX86_BUILTIN_RCP14SD,
- IX86_BUILTIN_RCP14SS, IX86_BUILTIN_RNDSCALESD,
+ new built-ins: <V2DF, V2DF, V2DF, INT, INT>,
+ <V4SF, V4SF, V4SF, INT, INT>, <(V4SF, V4SF, V2DF, INT>,
+ <V2DF, V2DF, V4SF, INT>, <V4SF, V4SF, V4SF, V4SF, IN>.
+ * config/i386/i386.c (enum ix86_builtins): Add
+ IX86_BUILTIN_ADDSD_ROUND, IX86_BUILTIN_ADDSS_ROUND,
+ IX86_BUILTIN_CVTSD2SS_ROUND, IX86_BUILTIN_CVTSS2SD_ROUND,
+ IX86_BUILTIN_DIVSD_ROUND, IX86_BUILTIN_GETEXPSD128,
+ IX86_BUILTIN_DIVSS_ROUND, IX86_BUILTIN_GETEXPSS128,
+ IX86_BUILTIN_GETMANTSD128, IX86_BUILTIN_GETMANTSS128,
+ IX86_BUILTIN_MAXSD_ROUND, IX86_BUILTIN_MAXSS_ROUND,
+ IX86_BUILTIN_MINSD_ROUND, IX86_BUILTIN_MINSS_ROUND,
+ IX86_BUILTIN_MULSD_ROUND, IX86_BUILTIN_MULSS_ROUND,
+ IX86_BUILTIN_RCP14SD, IX86_BUILTIN_RCP14SS, IX86_BUILTIN_RNDSCALESD,
IX86_BUILTIN_RNDSCALESS, IX86_BUILTIN_RSQRT14SD,
IX86_BUILTIN_RSQRT14SS, IX86_BUILTIN_SCALEFSD,
IX86_BUILTIN_SCALEFSS, IX86_BUILTIN_SQRTSD_ROUND,
@@ -752,7 +752,6 @@
(ix86_expand_int_vcond): Ditto.
(ix86_expand_vec_perm): Ditto.
(ix86_expand_sse_unpack): Ditto.
- (ix86_constant_alignment): Ditto.
(ix86_builtin_vectorized_function): Ditto.
(ix86_vectorize_builtin_gather): Ditto.
(avx_vpermilp_parallel): Ditto.
@@ -773,15 +772,15 @@
(ix86_autovectorize_vector_sizes): Ditto.
(ix86_expand_vec_perm_vpermi2): New.
(ix86_vector_duplicate_value): Ditto.
- (IX86_BUILTIN_SQRTPD512, IX86_BUILTIN_EXP2PS, IX86_BUILTIN_SQRTPS_NR512,
- IX86_BUILTIN_GATHER3ALTDIV16SF, IX86_BUILTIN_GATHER3ALTDIV16SI,
- IX86_BUILTIN_GATHER3ALTSIV8DF, IX86_BUILTIN_GATHER3ALTSIV8DI,
- IX86_BUILTIN_GATHER3DIV16SF, IX86_BUILTIN_GATHER3DIV16SI,
- IX86_BUILTIN_GATHER3DIV8DF, IX86_BUILTIN_GATHER3DIV8DI,
- IX86_BUILTIN_GATHER3SIV16SF, IX86_BUILTIN_GATHER3SIV16SI,
- IX86_BUILTIN_GATHER3SIV8DF, IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
- IX86_BUILTIN_CPYSGNPS512, IX86_BUILTIN_CPYSGNPD512,
- IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
+ (IX86_BUILTIN_SQRTPD512, IX86_BUILTIN_EXP2PS,
+ IX86_BUILTIN_SQRTPS_NR512, IX86_BUILTIN_GATHER3ALTDIV16SF,
+ IX86_BUILTIN_GATHER3ALTDIV16SI, IX86_BUILTIN_GATHER3ALTSIV8DF,
+ IX86_BUILTIN_GATHER3ALTSIV8DI, IX86_BUILTIN_GATHER3DIV16SF,
+ IX86_BUILTIN_GATHER3DIV16SI, IX86_BUILTIN_GATHER3DIV8DF,
+ IX86_BUILTIN_GATHER3DIV8DI, IX86_BUILTIN_GATHER3SIV16SF,
+ IX86_BUILTIN_GATHER3SIV16SI, IX86_BUILTIN_GATHER3SIV8DF,
+ IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, IX86_BUILTIN_CPYSGNPS512,
+ IX86_BUILTIN_CPYSGNPD512, IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512): Ditto.
* config/i386/sse.md (*mov<mode>_internal): Disable SSE typeless
stores vectors > 128bit (AVX*).
@@ -816,10 +815,8 @@
* config/nios2/constraints.md: New file.
* config/nios2/t-nios2: New file.
* common/config/nios2/nios2-common.c: New file.
- * doc/invoke.texi (Nios II options): Document Nios II specific
- options.
- * doc/md.texi (Nios II family): Document Nios II specific
- constraints.
+ * doc/invoke.texi (Nios II options): Document Nios II specific options.
+ * doc/md.texi (Nios II family): Document Nios II specific constraints.
* doc/extend.texi (Function Specific Option Pragmas): Document
Nios II supported target pragma functionality.
@@ -1076,8 +1073,8 @@
2013-12-26 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
- * config/i386/i386.c (get_builtin_code_for_version): Rename AMD
- CPU names M_AMD_BOBCAT to M_AMD_BTVER1 and M_AMD_JAGUAR
+ * config/i386/i386.c (get_builtin_code_for_version): Rename AMD
+ CPU names M_AMD_BOBCAT to M_AMD_BTVER1 and M_AMD_JAGUAR
to M_AMD_BTVER2.
(processor_model): Likewise.
(arch_names_table): Likewise.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 1fc68e144bb..39891c96402 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1568,7 +1568,7 @@ struct processor_costs nocona_cost = {
8, /* MMX or SSE register to integer */
8, /* size of l1 cache. */
1024, /* size of l2 cache. */
- 128, /* size of prefetch block */
+ 64, /* size of prefetch block */
8, /* number of parallel prefetches */
1, /* Branch cost */
COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
@@ -26465,8 +26465,16 @@ ix86_constant_alignment (tree exp, int align)
int
ix86_data_alignment (tree type, int align, bool opt)
{
- int max_align = optimize_size ? BITS_PER_WORD
- : MIN (512, MAX_OFILE_ALIGNMENT);
+ /* A data structure, equal or greater than the size of a cache line
+ (64 bytes in the Pentium 4 and other recent Intel processors, including
+ processors based on Intel Core microarchitecture) should be aligned
+ so that its base address is a multiple of a cache line size. */
+
+ int max_align
+ = MIN ((unsigned) ix86_tune_cost->prefetch_block * 8, MAX_OFILE_ALIGNMENT);
+
+ if (max_align < BITS_PER_WORD)
+ max_align = BITS_PER_WORD;
if (opt
&& AGGREGATE_TYPE_P (type)