diff options
| author | Yuliang Wang <yuliang.wang@arm.com> | 2019-09-30 16:55:45 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-09-30 16:55:45 +0000 |
| commit | c0c2f013906a695b8a02226f119649a370d9e083 (patch) | |
| tree | 6743c5d13bf23522c114e0de5e187c1dade8a1c4 /gcc/testsuite/lib/target-supports.exp | |
| parent | dcdd0f055731a8c960a15e5de8715d041d9a7876 (diff) | |
[AArch64][SVE] Utilize ASRD instruction for division and remainder
2019-09-30 Yuliang Wang <yuliang.wang@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (sdiv_pow2<mode>3):
New pattern for ASRD.
* config/aarch64/iterators.md (UNSPEC_ASRD): New unspec.
* internal-fn.def (IFN_DIV_POW2): New internal function.
* optabs.def (sdiv_pow2_optab): New optab.
* tree-vect-patterns.c (vect_recog_divmod_pattern):
Modify pattern to support new operation.
* doc/md.texi (sdiv_pow2$var{m3}): Documentation for the above.
* doc/sourcebuild.texi (vect_sdiv_pow2_si):
Document new target selector.
gcc/testsuite/
* gcc.dg/vect/vect-sdiv-pow2-1.c: New test.
* gcc.target/aarch64/sve/asrdiv_1.c: As above.
* lib/target-supports.exp (check_effective_target_vect_sdiv_pow2_si):
Return true for AArch64 with SVE.
From-SVN: r276343
Diffstat (limited to 'gcc/testsuite/lib/target-supports.exp')
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 0268acd91d8..a7b76b69b75 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -6256,6 +6256,14 @@ proc check_effective_target_vect_mulhrs_hi {} { && [check_effective_target_aarch64_sve2] }] } +# Return 1 if the target plus current options supports signed division +# by power-of-2 operations on vectors of 4-byte integers. + +proc check_effective_target_vect_sdiv_pow2_si {} { + return [expr { [istarget aarch64*-*-*] + && [check_effective_target_aarch64_sve] }] +} + # Return 1 if the target plus current options supports a vector # demotion (packing) of shorts (to chars) and ints (to shorts) # using modulo arithmetic, 0 otherwise. |