diff options
author | Kelvin Nilsen <kelvin@gcc.gnu.org> | 2020-05-11 16:25:03 -0500 |
---|---|---|
committer | Bill Schmidt <wschmidt@linux.ibm.com> | 2020-05-11 16:25:03 -0500 |
commit | 840ac85ced0695fefecee433327e4298b4adb20a (patch) | |
tree | 2ead3d269a344ed5865c2b409fdf5830c530eab1 /gcc/testsuite/gcc.target/powerpc/vec-ternarylogic-5.c | |
parent | 2202299c2aa69385ca5e7574914dabc84fb6a40a (diff) |
rs6000: Add xxeval and vec_ternarylogic
Add the xxeval insn and access it via the vec_ternarylogic built-in
function. As part of this, add support to the built-in function
infrastructure for functions that take four arguments.
[gcc]
2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
* config/rs6000/altivec.h (vec_ternarylogic): New #define.
* config/rs6000/altivec.md (UNSPEC_XXEVAL): New constant.
(xxeval): New insn.
* config/rs6000/predicates.md (u8bit_cint_operand): New predicate.
* config/rs6000/rs6000-builtin.def: Add handling of new macro
RS6000_BUILTIN_4.
(BU_FUTURE_V_4): New macro. Use it.
(BU_FUTURE_OVERLOAD_4): Likewise.
* config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Add
handling for quaternary built-in functions.
(altivec_resolve_overloaded_builtin): Add special-case handling
for __builtin_vec_xxeval.
* config/rs6000/rs6000-call.c: Add handling of new macro
RS6000_BUILTIN_4 in initialization of rs6000_builtin_info,
bdesc0_arg, bdesc1_arg, bdesc2_arg, bdesc_3arg,
bdesc_altivec_preds, bdesc_abs, and bdesc_htm arrays.
(altivec_overloaded_builtins): Add definitions for
FUTURE_BUILTIN_VEC_XXEVAL.
(bdesc_4arg): New array.
(htm_expand_builtin): Add handling for quaternary built-in
functions.
(rs6000_expand_quaternop_builtin): New function.
(rs6000_expand_builtin): Add handling for quaternary built-in
functions.
(rs6000_init_builtins): Initialize builtin_mode_to_type entries
for unsigned QImode and unsigned HImode.
(builtin_quaternary_function_type): New function.
(rs6000_common_init_builtins): Add handling of quaternary
operations.
* config/rs6000/rs6000.h (RS6000_BTC_QUATERNARY): New defined
constant.
(RS6000_BTC_PREDICATE): Change value of constant.
(RS6000_BTC_ABS): Likewise.
(rs6000_builtins): Add support for new macro RS6000_BUILTIN_4.
* doc/extend.texi (PowerPC AltiVec Built-In Functions Available
for a Future Architecture): Add description of vec_ternarylogic
built-in function.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
* gcc.target/powerpc/vec-ternarylogic-0.c: New.
* gcc.target/powerpc/vec-ternarylogic-1.c: New.
* gcc.target/powerpc/vec-ternarylogic-10.c: New.
* gcc.target/powerpc/vec-ternarylogic-2.c: New.
* gcc.target/powerpc/vec-ternarylogic-3.c: New.
* gcc.target/powerpc/vec-ternarylogic-4.c: New.
* gcc.target/powerpc/vec-ternarylogic-5.c: New.
* gcc.target/powerpc/vec-ternarylogic-6.c: New.
* gcc.target/powerpc/vec-ternarylogic-7.c: New.
* gcc.target/powerpc/vec-ternarylogic-8.c: New.
* gcc.target/powerpc/vec-ternarylogic-9.c: New.
Diffstat (limited to 'gcc/testsuite/gcc.target/powerpc/vec-ternarylogic-5.c')
-rw-r--r-- | gcc/testsuite/gcc.target/powerpc/vec-ternarylogic-5.c | 103 |
1 files changed, 103 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-ternarylogic-5.c b/gcc/testsuite/gcc.target/powerpc/vec-ternarylogic-5.c new file mode 100644 index 00000000000..4d5d8e5e0d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-ternarylogic-5.c @@ -0,0 +1,103 @@ +/* { dg-do run } */ +/* { dg-require-effective-target powerpc_future_hw } */ +/* { dg-options "-mdejagnu-cpu=future" } */ + +#include <altivec.h> + +extern void abort (void); + +#define NumSamples 4 + +void +doTests00000001 (vector unsigned int a_sources [], + vector unsigned int b_sources [], + vector unsigned int c_sources []) { + for (int i = 0; i < NumSamples; i++) + for (int j = 0; j < NumSamples; j++) + for (int k = 0; k < NumSamples; k++) + { + vector unsigned int a = a_sources [i]; + vector unsigned int b = b_sources [j]; + vector unsigned int c = c_sources [k]; + vector unsigned int result = vec_ternarylogic (a, b, c, 0x01); + vector unsigned int intended = (a & b & c); + if (!vec_all_eq (result, intended)) + abort (); + } +} + +void doTests11100101 (vector unsigned int a_sources [], + vector unsigned int b_sources [], + vector unsigned int c_sources []) { + for (int i = 0; i < NumSamples; i++) + for (int j = 0; j < NumSamples; j++) + for (int k = 0; k < NumSamples; k++) + { + vector unsigned int a = a_sources [i]; + vector unsigned int b = b_sources [j]; + vector unsigned int c = c_sources [k]; + vector unsigned int result = vec_ternarylogic (a, b, c, 0xe5); + vector unsigned int intended = { 0, 0, 0, 0 }; + // Supposed to be a ? c: nand (b,c) + for (int l = 0; l < 4; l++) + { + for (int m = 0; m < 32; m++) + { + unsigned int bit_selector = (0x01 << m); + if (a[l] & bit_selector) + intended [l] |= c [l] & bit_selector; + else if ((b [l] & c [l] & bit_selector) == 0) + intended [l] |= bit_selector; + } + } + if (!vec_all_eq (result, intended)) + abort (); + } +} + +void doTests11110011 (vector unsigned int a_sources [], + vector unsigned int b_sources [], + vector unsigned int c_sources []) { + for (int i = 0; i < NumSamples; i++) + for (int j = 0; j < NumSamples; j++) + for (int k = 0; k < NumSamples; k++) + { + vector unsigned int a = a_sources [i]; + vector unsigned int b = b_sources [j]; + vector unsigned int c = c_sources [k]; + vector unsigned int result = vec_ternarylogic (a, b, c, 0xfb); + vector unsigned int intended = { 0, 0, 0, 0 }; + for (int i = 0; i < 4; i++) + intended [i] = b [i] | ~(a [i] & c [i]); + if (!vec_all_eq (result, intended)) + abort (); + } +} + +int main (int argc, int *argv []) +{ + vector unsigned int a_sources [NumSamples] = { + { 0x01234567, 0x89abcdef, 0x12345678, 0x9abcdef0 }, + { 0x55555555, 0x55555555, 0xffffffff, 0xffffffff }, + { 0xcccccccc, 0x55555555, 0x00000000, 0x00000000 }, + { 0xe7e7e7e7, 0xe7e7e7e7, 0x69696969, 0x69696969 }, + }; + vector unsigned int b_sources [NumSamples] = { + { 0x01234567, 0x89abcdef, 0x12345678, 0x9abcdef0 }, + { 0x55555555, 0x55555555, 0xffffffff, 0xffffffff }, + { 0xcccccccc, 0x55555555, 0x00000000, 0x00000000 }, + { 0xe7e7e7e7, 0xe7e7e7e7, 0x69696969, 0x69696969 }, + }; + vector unsigned int c_sources [NumSamples] = { + { 0x01234567, 0x89abcdef, 0x12345678, 0x9abcdef0 }, + { 0x55555555, 0x55555555, 0xffffffff, 0xffffffff }, + { 0xcccccccc, 0x55555555, 0x00000000, 0x00000000 }, + { 0xe7e7e7e7, 0xe7e7e7e7, 0x69696969, 0x69696969 }, + }; + + doTests00000001 (a_sources, b_sources, c_sources); + doTests11100101 (a_sources, b_sources, c_sources); + doTests11110011 (a_sources, b_sources, c_sources); + + return 0; +} |