rs6000: Add vclrlb and vclrrb

Add new vector instructions to clear leftmost and rightmost bytes.

[gcc]

2020-05-11  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* config/rs6000/altivec.h (vec_clrl): New #define.
	(vec_clrr): Likewise.
	* config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant.
	(UNSPEC_VCLRRB): Likewise.
	(vclrlb): New insn.
	(vclrrb): Likewise.
	* config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New
	built-in function.
	(__builtin_altivec_vclrrb): Likewise.
	(__builtin_vec_clrl): New overloaded built-in function.
	(__builtin_vec_clrr): Likewise.
	* config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
	Define overloaded forms of __builtin_vec_clrl and
	__builtin_vec_clrr.
	* doc/extend.texi (PowerPC AltiVec Built-in Functions Available
	for a Future Architecture): Add descriptions of vec_clrl and
	vec_clrr.

[gcc/testsuite]

2020-05-11  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* gcc.target/powerpc/vec-clrl-0.c: New.
	* gcc.target/powerpc/vec-clrl-1.c: New.
	* gcc.target/powerpc/vec-clrr-0.c: New.
	* gcc.target/powerpc/vec-clrr-1.c: New.

1 files changed, 37 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/powerpc/vec-clrl-3.c b/gcc/testsuite/gcc.target/powerpc/vec-clrl-3.c
new file mode 100644
index 00000000000..582eb1cfd12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-clrl-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_future_hw } */
+/* { dg-options "-mdejagnu-cpu=future" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+/* Vector string clear left-most bytes of unsigned char.  */
+vector signed char
+clrl (vector signed char arg, int n)
+{
+  return vec_clrl (arg, n);
+}
+
+int main (int argc, char *argv [])
+{
+  vector signed char input0 =
+    { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+      0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+  vector signed char expected0 =
+    { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+      0x0, 0x0, 0x0, 0xc, 0xd, 0xe, 0xf, 0x11 };
+  vector signed char expected1 =
+    { 0x0, 0x0, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
+      0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+  vector signed char expected2 =
+    { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+      0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+
+  if (!vec_all_eq (clrl (input0, 5), expected0))
+    abort ();
+  if (!vec_all_eq (clrl (input0, 13), expected1))
+    abort ();
+  if (!vec_all_eq (clrl (input0, 19), expected2))
+    abort ();
+}