diff options
| author | Kelvin Nilsen <kelvin@gcc.gnu.org> | 2020-05-11 16:09:53 -0500 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.ibm.com> | 2020-05-11 16:09:53 -0500 |
| commit | 25bf7d32c31bb45993a9c81dd01043e77c4a44ed (patch) | |
| tree | c97e5bc9c588f93bcc32b5ffe629ee65eb949abe /gcc/testsuite/gcc.target/powerpc/vec-clrl-2.c | |
| parent | 0e47fe3ab528c1b29305bfd4ac3889703b4fd85c (diff) | |
rs6000: Add vclrlb and vclrrb
Add new vector instructions to clear leftmost and rightmost bytes.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/altivec.h (vec_clrl): New #define.
(vec_clrr): Likewise.
* config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant.
(UNSPEC_VCLRRB): Likewise.
(vclrlb): New insn.
(vclrrb): Likewise.
* config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New
built-in function.
(__builtin_altivec_vclrrb): Likewise.
(__builtin_vec_clrl): New overloaded built-in function.
(__builtin_vec_clrr): Likewise.
* config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
Define overloaded forms of __builtin_vec_clrl and
__builtin_vec_clrr.
* doc/extend.texi (PowerPC AltiVec Built-in Functions Available
for a Future Architecture): Add descriptions of vec_clrl and
vec_clrr.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/vec-clrl-0.c: New.
* gcc.target/powerpc/vec-clrl-1.c: New.
* gcc.target/powerpc/vec-clrr-0.c: New.
* gcc.target/powerpc/vec-clrr-1.c: New.
Diffstat (limited to 'gcc/testsuite/gcc.target/powerpc/vec-clrl-2.c')
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/vec-clrl-2.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-clrl-2.c b/gcc/testsuite/gcc.target/powerpc/vec-clrl-2.c new file mode 100644 index 00000000000..265fe7817f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-clrl-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=future" } */ + +#include <altivec.h> + +extern void abort (void); + +/* Vector string clear left-most bytes of unsigned char. */ +vector signed char +clrl (vector signed char arg, int n) +{ + return vec_clrl (arg, n); +} + +/* { dg-final { scan-assembler {\mvclrlb\M} { target be } } } */ +/* { dg-final { scan-assembler {\mvclrrb\M} { target le } } } */ |