diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2014-10-22 12:02:26 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2014-10-22 12:02:26 +0000 |
| commit | daca1a96afae35e1a2f39b91f014c2f414f70c5f (patch) | |
| tree | eee5382fbf8bb42300717bebf986a46d87ae8a9f /gcc/postreload-gcse.c | |
| parent | 9840b2fa87cc9657dca2b63dc66d37f94d2c9cb8 (diff) | |
recog.h (constrain_operands): Add an alternative_mask parameter.
gcc/
* recog.h (constrain_operands): Add an alternative_mask parameter.
(constrain_operands_cached): Likewise.
(get_preferred_alternatives): Declare new form.
* recog.c (get_preferred_alternatives): New bb-taking instance.
(constrain_operands): Take the set of available alternatives as
a parameter.
(check_asm_operands, insn_invalid_p, extract_constrain_insn)
(extract_constrain_insn_cached): Update calls to constrain_operands.
* caller-save.c (reg_save_code): Likewise.
* ira.c (setup_prohibited_mode_move_regs): Likewise.
* postreload-gcse.c (eliminate_partially_redundant_load): Likewise.
* ree.c (combine_reaching_defs): Likewise.
* reload.c (can_reload_into): Likewise.
* reload1.c (reload, reload_as_needed, inc_for_reload): Likewise.
(gen_reload_chain_without_interm_reg_p, emit_input_reload_insns)
(emit_insn_if_valid_for_reload): Likewise.
* reorg.c (fill_slots_from_thread): Likewise.
* config/i386/i386.c (ix86_attr_length_address_default): Likewise.
* config/pa/pa.c (pa_can_combine_p): Likewise.
* config/rl78/rl78.c (insn_ok_now): Likewise.
* config/sh/sh.md (define_peephole2): Likewise.
* final.c (final_scan_insn): Update call to constrain_operands_cached.
From-SVN: r216555
Diffstat (limited to 'gcc/postreload-gcse.c')
| -rw-r--r-- | gcc/postreload-gcse.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/gcc/postreload-gcse.c b/gcc/postreload-gcse.c index 03b054a30cd..264e03064f8 100644 --- a/gcc/postreload-gcse.c +++ b/gcc/postreload-gcse.c @@ -1008,10 +1008,11 @@ eliminate_partially_redundant_load (basic_block bb, rtx_insn *insn, /* Make sure we can generate a move from register avail_reg to dest. */ - extract_insn (as_a <rtx_insn *> ( - gen_move_insn (copy_rtx (dest), - copy_rtx (avail_reg)))); - if (! constrain_operands (1) + rtx_insn *move = as_a <rtx_insn *> + (gen_move_insn (copy_rtx (dest), copy_rtx (avail_reg))); + extract_insn (move); + if (! constrain_operands (1, get_preferred_alternatives (insn, + pred_bb)) || reg_killed_on_edge (avail_reg, pred) || reg_used_on_edge (dest, pred)) { |