summaryrefslogtreecommitdiff
path: root/gcc/lra-int.h
diff options
context:
space:
mode:
authorVladimir Makarov <vmakarov@redhat.com>2015-04-09 19:40:09 +0000
committerVladimir Makarov <vmakarov@gcc.gnu.org>2015-04-09 19:40:09 +0000
commit8fd827b8e58b04cdefeb3d5c4de4d53566fdc3ff (patch)
tree9684a6d40e6a42b869a0f236d04ab6c6882b0ca8 /gcc/lra-int.h
parentbf1b77dd092bb694be6fb0b1fcc369327db6143f (diff)
re PR target/65710 (Thumb1 ICE caused by no register to spill)
2015-04-09 Vladimir Makarov <vmakarov@redhat.com> PR target/65710 * lra-int.h (lra_bad_spill_regno_start): New. * lra.c (lra_bad_spill_regno_start): New. (lra): Set up lra_bad_spill_regno_start. Set up lra_constraint_new_regno_start unconditionally. * lra-assigns.c (spill_for): Use lra_bad_spill_regno_start for spill preferences. From-SVN: r221956
Diffstat (limited to 'gcc/lra-int.h')
-rw-r--r--gcc/lra-int.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/gcc/lra-int.h b/gcc/lra-int.h
index c6b147e6f78..12923ee216a 100644
--- a/gcc/lra-int.h
+++ b/gcc/lra-int.h
@@ -333,6 +333,7 @@ extern void lra_register_new_scratch_op (rtx_insn *, int);
extern int lra_new_regno_start;
extern int lra_constraint_new_regno_start;
+extern int lra_bad_spill_regno_start;
extern bitmap_head lra_inheritance_pseudos;
extern bitmap_head lra_split_regs;
extern bitmap_head lra_subreg_reload_pseudos;