rs6000: Built-in cleanups for vec_clzm, vec_ctzm, and vec_gnb

Changes to the built-in specification occurred after early patches
added support for these.  The name of vec_clzm became vec_cntlzm,
and vec_ctzm became vec_cnttzm.  Four of the overloaded forms of
vec_gnb were removed, and the fourth argument redefined as an
unsigned int, not an unsigned char.  This patch reflects those
changes in the code and test cases.  Eight of the vec_gnb test
cases are removed as a result.

[gcc]

2020-05-11  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* config/rs6000/altivec.h (vec_clzm): Rename to vec_cntlzm.
	(vec_ctzm): Rename to vec_cnttzm.
	* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
	Change fourth operand for vec_ternarylogic to require
	compatibility with unsigned SImode rather than unsigned QImode.
	* config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
	Remove overloaded forms of vec_gnb that are no longer needed.
	* doc/extend.texi (PowerPC AltiVec Built-in Functions Available
	for a Future Architecture): Replace vec_clzm with vec_cntlzm;
	replace vec_ctzm with vec_cntlzm; remove four unwanted forms of
	vec_gnb; move vec_ternarylogic documentation into this section
	and replace const unsigned char with const unsigned int as its
	fourth argument.

[gcc/testsuite]

2020-05-11  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* gcc.target/powerpc/vec-clzm-0.c: Rename to...
	* gcc.target/powerpc/vec-cntlzm-0.c: ...this.
	* gcc.target/powerpc/vec-clzm-1.c: Rename to...
	* gcc.target/powerpc/vec-cntlzm-1.c: ...this.
	* gcc.target/powerpc/vec-ctzm-0.c: Rename to...
	* gcc.target/powerpc/vec-cnttzm-0.c: ...this.
	* gcc.target/powerpc/vec-ctzm-1.c: Rename to...
	* gcc.target/powerpc/vec-cnttzm-1.c: ...this.
	* gcc.target/powerpc/vec-gnb-8.c: Rename to...
	* gcc.target/powerpc/vec-gnb-0.c: ...this, deleting the old file.
	* gcc.target/powerpc/vec-gnb-9.c: Rename to...
	* gcc.target/powerpc/vec-gnb-1.c: ...this, deleting the old file.
	* gcc.target/powerpc/vec-gnb-10.c: Rename to...
	* gcc.target/powerpc/vec-gnb-2.c: ...this, deleting the old file.
	* gcc.target/powerpc/vec-gnb-3.c: Delete.
	* gcc.target/powerpc/vec-gnb-4.c: Delete.
	* gcc.target/powerpc/vec-gnb-5.c: Delete.
	* gcc.target/powerpc/vec-gnb-6.c: Delete.
	* gcc.target/powerpc/vec-gnb-7.c: Delete.

1 files changed, 26 insertions, 34 deletions

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index c352c512285..4c5ed3f3bac 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -20762,19 +20762,19 @@ Perform a vector centrifuge operation, as if implemented by the Future
 
 @smallexample
 @exdent vector unsigned long long int
-@exdent vec_clzm (vector unsigned long long int, vector unsigned long long int)
+@exdent vec_cntlzm (vector unsigned long long int, vector unsigned long long int)
 @end smallexample
 Perform a vector count leading zeros under bit mask operation, as if
 implemented by the Future @code{vclzdm} instruction.
-@findex vec_clzm
+@findex vec_cntlzm
 
 @smallexample
 @exdent vector unsigned long long int
-@exdent vec_ctzm (vector unsigned long long int, vector unsigned long long int)
+@exdent vec_cnttzm (vector unsigned long long int, vector unsigned long long int)
 @end smallexample
 Perform a vector count trailing zeros under bit mask operation, as if
 implemented by the Future @code{vctzdm} instruction.
-@findex vec_ctzm
+@findex vec_cnttzm
 
 @smallexample
 @exdent vector signed char
@@ -20802,14 +20802,6 @@ value of @code{n} that is greater than 16 is treated as if it equaled 16.
 
 @smallexample
 @exdent vector unsigned long long int
-@exdent vec_gnb (vector unsigned char, const unsigned char)
-@exdent vector unsigned long long int
-@exdent vec_gnb (vector unsigned short, const unsigned char)
-@exdent vector unsigned long long int
-@exdent vec_gnb (vector unsigned int, const unsigned char)
-@exdent vector unsigned long long int
-@exdent vec_gnb (vector unsigned long long int, const unsigned char)
-@exdent vector unsigned long long int
 @exdent vec_gnb (vector unsigned __int128, const unsigned char)
 @end smallexample
 Perform a 128-bit vector gather  operation, as if implemented by the Future
@@ -20890,6 +20882,28 @@ zero element if the same argument is also passed to @code{vec_strir}.
 @findex vec_strir_p
 
 @smallexample
+@exdent vector unsigned char
+@exdent vec_ternarylogic (vector unsigned char, vector unsigned char,
+            vector unsigned char, const unsigned int)
+@exdent vector unsigned short
+@exdent vec_ternarylogic (vector unsigned short, vector unsigned short,
+            vector unsigned short, const unsigned int)
+@exdent vector unsigned int
+@exdent vec_ternarylogic (vector unsigned int, vector unsigned int,
+            vector unsigned int, const unsigned int)
+@exdent vector unsigned long long int
+@exdent vec_ternarylogic (vector unsigned long long int, vector unsigned long long int,
+            vector unsigned long long int, const unsigned int)
+@exdent vector unsigned __int128
+@exdent vec_ternarylogic (vector unsigned __int128, vector unsigned __int128,
+            vector unsigned __int128, const unsigned int)
+@end smallexample
+Perform a 128-bit vector evaluate operation, as if implemented by the
+Future @code{xxeval} instruction.  The fourth argument must be a literal
+integer value between 0 and 255 inclusive.
+@findex vec_ternarylogic
+
+@smallexample
 @exdent vector unsigned char vec_genpcvm (vector unsigned char, const int)
 @exdent vector unsigned short vec_genpcvm (vector unsigned short, const int)
 @exdent vector unsigned int vec_genpcvm (vector unsigned int, const int)
@@ -22123,28 +22137,6 @@ else
 @end smallexample
 @end deftypefn
 
-@smallexample
-@exdent vector unsigned char
-@exdent vec_ternarylogic (vector unsigned char, vector unsigned char,
-            vector unsigned char, const unsigned char)
-@exdent vector unsigned short
-@exdent vec_ternarylogic (vector unsigned short, vector unsigned short,
-            vector unsigned short, const unsigned char)
-@exdent vector unsigned int
-@exdent vec_ternarylogic (vector unsigned int, vector unsigned int,
-            vector unsigned int, const unsigned char)
-@exdent vector unsigned long long int
-@exdent vec_ternarylogic (vector unsigned long long int, vector unsigned long long int,
-            vector unsigned long long int, const unsigned char)
-@exdent vector unsigned __int128
-@exdent vec_ternarylogic (vector unsigned __int128, vector unsigned __int128,
-            vector unsigned __int128, const unsigned char)
-@end smallexample
-Perform a 128-bit vector evaluate operation, as if implemented by the
-Future @code{xxeval} instruction.  The fourth argument must be a literal
-integer value between 0 and 255 inclusive.
-@findex vec_ternarylogic
-
 The following built-in functions are made available by @option{-mmmx}.
 All of them generate the machine instruction that is part of the name.