diff options
| author | Segher Boessenkool <segher@kernel.crashing.org> | 2019-05-22 00:03:37 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2019-05-22 00:03:37 +0200 |
| commit | fae803b2db46b8baf1610948fea344475974b7da (patch) | |
| tree | 6cd1fa1f00a4fc40bed7633dab4d8605bd47d37e /gcc/config/rs6000/rs6000.md | |
| parent | 5007f60b33a58edbcba399b7e5083553bf604faf (diff) | |
rs6000: wh -> d+p8v
This replaces the "wh" constraint by "d", with isa "p8v".
* config/rs6000/constraints.md (define_register_constraint "wh"):
Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wh.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.md: Replace "wh" constraint by "wa" with "p8v".
* doc/md.texi (Machine Constraints): Adjust.
From-SVN: r271483
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b2bba5d004c..398398ca8cf 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -471,7 +471,7 @@ (define_mode_attr f64_vsx [(DF "ws") (DD "wn")]) ; Definitions for 64-bit direct move -(define_mode_attr f64_dm [(DF "wk") (DD "wh")]) +(define_mode_attr f64_dm [(DF "wk") (DD "d")]) ; Definitions for 64-bit use of altivec registers (define_mode_attr f64_av [(DF "wv") (DD "wn")]) @@ -7349,10 +7349,10 @@ ;; FMR MR MT%0 MF%1 NOP (define_insn "movsd_hardfloat" [(set (match_operand:SD 0 "nonimmediate_operand" - "=!r, wz, m, Z, ?wh, ?r, + "=!r, wz, m, Z, ?d, ?r, f, !r, *c*l, !r, *h") (match_operand:SD 1 "input_operand" - "m, Z, r, wx, r, wh, + "m, Z, r, wx, r, d, f, r, r, *h, 0"))] "(register_operand (operands[0], SDmode) || register_operand (operands[1], SDmode)) @@ -7371,7 +7371,10 @@ nop" [(set_attr "type" "load, fpload, store, fpstore, mffgpr, mftgpr, - fpsimple, *, mtjmpr, mfjmpr, *")]) + fpsimple, *, mtjmpr, mfjmpr, *") + (set_attr "isa" + "*, *, *, *, p8v, p8v, + *, *, *, *, *")]) ;; MR MT%0 MF%0 LWZ STW LI ;; LIS G-const. F/n-const NOP @@ -7684,7 +7687,7 @@ "*, *, *, p9v, p9v, *, *, *, *, *, *, *, *, *, *, - *, *, *, *, *")]) + *, *, *, p8v, p8v")]) ;; STD LD MR MT<SPR> MF<SPR> G-const ;; H-const F-const Special @@ -7737,8 +7740,8 @@ ;; problematical. Don't allow direct move for this case. (define_insn_and_split "*mov<mode>_64bit_dm" - [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r,r,wh") - (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r,wh,r"))] + [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r,r,d") + (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r,d,r"))] "TARGET_HARD_FLOAT && TARGET_POWERPC64 && FLOAT128_2REG_P (<MODE>mode) && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN) && (gpc_reg_operand (operands[0], <MODE>mode) @@ -7747,7 +7750,8 @@ "&& reload_completed" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,8,8,12,12,8,8,8")]) + [(set_attr "length" "8,8,8,8,12,12,8,8,8") + (set_attr "isa" "*,*,*,*,*,*,*,p8v,p8v")]) (define_insn_and_split "*movtd_64bit_nodm" [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r") |