rs6000: ws -> wa

"ws" is just "wa".


	* config/rs6000/constraints.md (define_register_constraint "ws"):
	Delete.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
	(rs6000_init_hard_regno_mode_ok): Adjust.
	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
	RS6000_CONSTRAINT_ws.
	* config/rs6000/rs6000.md: Adjust.
	* config/rs6000/vsx.md: Adjust.
	* doc/md.texi (Machine Constraints): Adjust.

From-SVN: r271916

1 files changed, 15 insertions, 15 deletions

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 45e03479b77..a0628c12b52 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -469,10 +469,10 @@
 			   (TD "wn")])
 
 ; Definitions for 64-bit VSX
-(define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
+(define_mode_attr f64_vsx [(DF "wa") (DD "wn")])
 
 ; Definitions for 64-bit direct move
-(define_mode_attr f64_dm  [(DF "ws") (DD "d")])
+(define_mode_attr f64_dm  [(DF "wa") (DD "d")])
 
 ; Definitions for 64-bit use of altivec registers
 (define_mode_attr f64_av  [(DF "v") (DD "wn")])
@@ -526,12 +526,12 @@
 ; ISA 2.06 (power7).  This includes instructions that normally target DF mode,
 ; but are used on SFmode, since internally SFmode values are kept in the DFmode
 ; format.
-(define_mode_attr Fv		[(SF "ww") (DF "ws") (DI "wa")])
+(define_mode_attr Fv		[(SF "ww") (DF "wa") (DI "wa")])
 
 ; SF/DF constraint for arithmetic on VSX registers.  This is intended to be
 ; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
 ; instructions added in ISA 2.07 (power8)
-(define_mode_attr Fv2		[(SF "wa") (DF "ws") (DI "wa")])
+(define_mode_attr Fv2		[(SF "wa") (DF "wa") (DI "wa")])
 
 ; Which isa is needed for those float instructions?
 (define_mode_attr Fisa		[(SF "p8v")  (DF "*") (DI "*")])
@@ -626,7 +626,7 @@
 			(DI "Y")])
 
 (define_mode_attr rreg [(SF   "f")
-			(DF   "ws")
+			(DF   "wa")
 			(TF   "f")
 			(TD   "f")
 			(V4SF "wf")
@@ -4783,7 +4783,7 @@
 })
 
 (define_insn_and_split "*extendsfdf2_fpr"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wa,v")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,wa,?wa,wa,v")
 	(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wa,Z,wY")))]
   "TARGET_HARD_FLOAT && !HONOR_SNANS (SFmode)"
   "@
@@ -4804,7 +4804,7 @@
    (set_attr "isa" "*,*,*,*,p8v,p8v,p9v")])
 
 (define_insn "*extendsfdf2_snan"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f,wa")))]
   "TARGET_HARD_FLOAT && HONOR_SNANS (SFmode)"
   "@
@@ -4821,7 +4821,7 @@
 
 (define_insn "*truncdfsf2_fpr"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
-	(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,ws")))]
+	(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    frsp %0,%1
@@ -6027,8 +6027,8 @@
 ;; since the friz instruction does not truncate the value if the floating
 ;; point value is < LONG_MIN or > LONG_MAX.
 (define_insn "*friz"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
-	(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
+	(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))]
   "TARGET_HARD_FLOAT && TARGET_FPRND
    && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
   "@
@@ -6223,7 +6223,7 @@
 })
 
 (define_insn "floatdidf2"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_FCFID && TARGET_HARD_FLOAT"
   "@
@@ -6237,7 +6237,7 @@
 ; hit.  We will split after reload to avoid the trip through the GPRs
 
 (define_insn_and_split "*floatdidf2_mem"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
    (clobber (match_scratch:DI 2 "=d,wa"))]
   "TARGET_HARD_FLOAT && TARGET_FCFID"
@@ -6257,7 +6257,7 @@
   "")
 
 (define_insn "*floatunsdidf2_fcfidu"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT && TARGET_FCFIDU"
   "@
@@ -6266,7 +6266,7 @@
   [(set_attr "type" "fp")])
 
 (define_insn_and_split "*floatunsdidf2_mem"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
    (clobber (match_scratch:DI 2 "=d,wa"))]
   "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
@@ -7855,7 +7855,7 @@
 (define_insn_and_split "extenddf<mode>2_vsx"
   [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d")
 	(float_extend:IBM128
-	 (match_operand:DF 1 "nonimmediate_operand" "ws,m")))]
+	 (match_operand:DF 1 "nonimmediate_operand" "wa,m")))]
   "TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (<MODE>mode)"
   "#"
   "&& reload_completed"