rs6000: Delete the "wy" constraint

This replaces the "wy" constraint by "wa", with isa "p8v".  It also
creates a new attribute <Fisa>, used together with all <Fv2>.


	* config/rs6000/constraints.md (define_register_constraint "wy"):
	Delete.
	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
	RS6000_CONSTRAINT_wy.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
	(rs6000_init_hard_regno_mode_ok): Adjust.
	* config/rs6000/rs6000.md: Replace "wy" constraint by "wa" with "p8v".
	Use "<Fisa>" as "isa" in all alternatives that use "<Fv2>".
	(define_mode_attr Fisa): New.
	* config/rs6000/vsx.md: Replace "wy" constraint by "wa" with "p8v".
	* doc/md.texi (Machine Constraints): Adjust.

From-SVN: r271389

1 files changed, 52 insertions, 32 deletions

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c5def7480d9..984fe9ee40c 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -530,7 +530,10 @@
 ; SF/DF constraint for arithmetic on VSX registers.  This is intended to be
 ; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
 ; instructions added in ISA 2.07 (power8)
-(define_mode_attr Fv2		[(SF "wy") (DF "ws") (DI "wi")])
+(define_mode_attr Fv2		[(SF "wa") (DF "ws") (DI "wi")])
+
+; Which isa is needed for those float instructions?
+(define_mode_attr Fisa		[(SF "p8v")  (DF "*") (DI "*")])
 
 ; s/d suffix for things like sdiv/ddiv
 (define_mode_attr Fs		[(SF "s")  (DF "d")])
@@ -4641,7 +4644,8 @@
   "@
    fadd<Ftrad> %0,%1,%2
    xsadd<Fvsx> %x0,%x1,%x2"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_expand "sub<mode>3"
   [(set (match_operand:SFDF 0 "gpc_reg_operand")
@@ -4658,7 +4662,8 @@
   "@
    fsub<Ftrad> %0,%1,%2
    xssub<Fvsx> %x0,%x1,%x2"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_expand "mul<mode>3"
   [(set (match_operand:SFDF 0 "gpc_reg_operand")
@@ -4675,7 +4680,8 @@
   "@
    fmul<Ftrad> %0,%1,%2
    xsmul<Fvsx> %x0,%x1,%x2"
-  [(set_attr "type" "dmul")])
+  [(set_attr "type" "dmul")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_expand "div<mode>3"
   [(set (match_operand:SFDF 0 "gpc_reg_operand")
@@ -4700,7 +4706,8 @@
   "@
    fdiv<Ftrad> %0,%1,%2
    xsdiv<Fvsx> %x0,%x1,%x2"
-  [(set_attr "type" "<Fs>div")])
+  [(set_attr "type" "<Fs>div")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_insn "*sqrt<mode>2_internal"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
@@ -4709,7 +4716,8 @@
   "@
    fsqrt<Ftrad> %0,%1
    xssqrt<Fvsx> %x0,%x1"
-  [(set_attr "type" "<Fs>sqrt")])
+  [(set_attr "type" "<Fs>sqrt")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_expand "sqrt<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand")
@@ -4737,7 +4745,8 @@
   "@
    fre<Ftrad> %0,%1
    xsre<Fvsx> %x0,%x1"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_insn "*rsqrt<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
@@ -4747,7 +4756,8 @@
   "@
    frsqrte<Ftrad> %0,%1
    xsrsqrte<Fvsx> %x0,%x1"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>")])
 
 ;; Floating point comparisons
 (define_insn "*cmp<mode>_fpr"
@@ -4758,7 +4768,8 @@
   "@
    fcmpu %0,%1,%2
    xscmpudp %0,%x1,%x2"
-  [(set_attr "type" "fpcompare")])
+  [(set_attr "type" "fpcompare")
+   (set_attr "isa" "*,<Fisa>")])
 
 ;; Floating point conversions
 (define_expand "extendsfdf2"
@@ -4772,7 +4783,7 @@
 
 (define_insn_and_split "*extendsfdf2_fpr"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wa,v")
-	(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z,wY")))]
+	(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wa,Z,wY")))]
   "TARGET_HARD_FLOAT && !HONOR_SNANS (SFmode)"
   "@
    #
@@ -4789,16 +4800,17 @@
   DONE;
 }
   [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")
-   (set_attr "isa" "*,*,*,*,*,p8v,p9v")])
+   (set_attr "isa" "*,*,*,*,p8v,p8v,p9v")])
 
 (define_insn "*extendsfdf2_snan"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
-	(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f,wy")))]
+	(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f,wa")))]
   "TARGET_HARD_FLOAT && HONOR_SNANS (SFmode)"
   "@
    frsp %0,%1
    xsrsp %x0,%x1"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,p8v")])
 
 (define_expand "truncdfsf2"
   [(set (match_operand:SF 0 "gpc_reg_operand")
@@ -4807,13 +4819,14 @@
   "")
 
 (define_insn "*truncdfsf2_fpr"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
 	(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,ws")))]
   "TARGET_HARD_FLOAT"
   "@
    frsp %0,%1
    xsrsp %x0,%x1"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,p8v")])
 
 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
 ;; builtins.c and optabs.c that are not correct for IBM long double
@@ -6288,16 +6301,17 @@
 })
 
 (define_insn "floatdisf2_fcfids"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
 	(float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
   "TARGET_HARD_FLOAT && TARGET_FCFIDS"
   "@
    fcfids %0,%1
    xscvsxdsp %x0,%x1"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,p8v")])
 
 (define_insn_and_split "*floatdisf2_mem"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
 	(float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
    (clobber (match_scratch:DI 2 "=d,d,wi"))]
   "TARGET_HARD_FLOAT && TARGET_FCFIDS"
@@ -6309,7 +6323,8 @@
   emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
   DONE;
 }
-  [(set_attr "length" "8")])
+  [(set_attr "length" "8")
+   (set_attr "isa" "*,p8v,p8v")])
 
 ;; This is not IEEE compliant if rounding mode is "round to nearest".
 ;; If the DI->DF conversion is inexact, then it's possible to suffer
@@ -6377,7 +6392,7 @@
    (set_attr "isa" "*,p8v")])
 
 (define_insn_and_split "*floatunsdisf2_mem"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
 	(unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
    (clobber (match_scratch:DI 2 "=d,d,wi"))]
   "TARGET_HARD_FLOAT && TARGET_FCFIDUS"
@@ -6389,8 +6404,9 @@
   emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
   DONE;
 }
-  [(set_attr "length" "8")
-   (set_attr "type" "fpload")])
+  [(set_attr "type" "fpload")
+   (set_attr "length" "8")
+   (set_attr "isa" "*,p8v,p8v")])
 
 ;; Define the TImode operations that can be done in a small number
 ;; of instructions.  The & constraints are to prevent the register
@@ -7410,10 +7426,10 @@
 (define_insn_and_split "movsf_from_si"
   [(set (match_operand:SF 0 "nonimmediate_operand"
 	    "=!r,       f,         v,         wa,        m,         Z,
-	     Z,         wy,        ?r,        !r")
+	     Z,         wa,        ?r,        !r")
 	(unspec:SF [(match_operand:SI 1 "input_operand" 
 	    "m,         m,         wY,        Z,         r,         f,
-	     wa,        r,         wy,        r")]
+	     wa,        r,         wa,        r")]
 		   UNSPEC_SF_FROM_SI))
    (clobber (match_scratch:DI 2
 	    "=X,        X,         X,         X,         X,         X,
@@ -7457,7 +7473,7 @@
 	     fpstore,    vecfloat,  mffgpr,    *")
    (set_attr "isa"
 	    "*,          *,         p9v,       p8v,       *,         *,
-	     p8v,        *,         *,         *")])
+	     p8v,        p8v,       p8v,       *")])
 
 
 ;; Move 64-bit binary/decimal floating point
@@ -13301,7 +13317,8 @@
    fmadd<Ftrad> %0,%1,%2,%3
    xsmadda<Fvsx> %x0,%x1,%x2
    xsmaddm<Fvsx> %x0,%x1,%x3"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>,<Fisa>")])
 
 ; Altivec only has fma and nfms.
 (define_expand "fms<mode>4"
@@ -13324,7 +13341,8 @@
    fmsub<Ftrad> %0,%1,%2,%3
    xsmsuba<Fvsx> %x0,%x1,%x2
    xsmsubm<Fvsx> %x0,%x1,%x3"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>,<Fisa>")])
 
 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
 (define_expand "fnma<mode>4"
@@ -13371,7 +13389,8 @@
    fnmadd<Ftrad> %0,%1,%2,%3
    xsnmadda<Fvsx> %x0,%x1,%x2
    xsnmaddm<Fvsx> %x0,%x1,%x3"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>,<Fisa>")])
 
 ; Not an official optab name, but used from builtins.
 (define_expand "nfms<mode>4"
@@ -13397,8 +13416,8 @@
    fnmsub<Ftrad> %0,%1,%2,%3
    xsnmsuba<Fvsx> %x0,%x1,%x2
    xsnmsubm<Fvsx> %x0,%x1,%x3"
-  [(set_attr "type" "fp")])
-
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>,<Fisa>")])
 
 (define_expand "rs6000_get_timebase"
   [(use (match_operand:DI 0 "gpc_reg_operand"))]
@@ -14022,7 +14041,7 @@
 ;; the KFmode -> DFmode conversion using round to odd rather than the normal
 ;; conversion
 (define_insn_and_split "trunc<mode>sf2_hw"
-  [(set (match_operand:SF 0 "vsx_register_operand" "=wy")
+  [(set (match_operand:SF 0 "vsx_register_operand" "=wa")
 	(float_truncate:SF
 	 (match_operand:IEEE128 1 "altivec_register_operand" "v")))
    (clobber (match_scratch:DF 2 "=v"))]
@@ -14039,7 +14058,8 @@
     operands[2] = gen_reg_rtx (DFmode);
 }
   [(set_attr "type" "vecfloat")
-   (set_attr "length" "8")])
+   (set_attr "length" "8")
+   (set_attr "isa" "p8v")])
 
 ;; Conversion between IEEE 128-bit and integer types