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ampere-computing/binutils-gdb.git
binutils-2_30-amp-branch
binutils-2_31_1-amp-branch
binutils-2_32-amp-branch
binutils-2_34-amp-branch
gdb-8.1-amp-branch
gdb-8.2.1-amp-branch
gdb-9.1-amp-branch
Binutils/GDB including Ampere Computing toolchain specific patches
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opcodes
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riscv-opc.c
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Author
2018-01-03
Update year range in copyright notice of binutils files
Alan Modra
2017-12-20
RISC-V: Add compressed instruction hints, and a few misc cleanups.
Jim Wilson
2017-12-13
Add missing RISC-V fsrmi and fsflagsi instructions.
Jim Wilson
2017-10-24
RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0
Andrew Waterman
2017-09-27
Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...
Nick Clifton
2017-08-22
RISC-V: Mark "c.nop" as an alias
Palmer Dabbelt
2017-06-23
RISC-V: Fix SLTI disassembly
Andrew Waterman
2017-05-02
RISC-V: Change CALL macro to use ra as the temporary address register
Michael Clark
2017-03-15
RISC-V: Fix assembler for c.li, c.andi and c.addiw
Kito Cheng
2017-03-15
RISC-V: Fix assembler for c.addi, rd can be x0
Kito Cheng
2017-03-14
RISC-V: Fix [dis]assembly of srai/srli
Andrew Waterman
2017-02-15
Add SFENCE.VMA instruction
Andrew Waterman
2017-01-03
Add support for the Q extension to the RISCV ISA.
Kito Cheng
2017-01-02
Update year range in copyright notice of all files.
Alan Modra
2016-12-22
Avoid creating symbol table entries for registers
Andrew Waterman
2016-12-20
Correct assembler mnemonic for RISC-V aqrl AMOs
Andrew Waterman
2016-12-20
Fix disassembly of RISC-V CSR instructions under -Mno-aliases
Andrew Waterman
2016-12-20
Add canonical JALR for RISC-V
Andrew Waterman
2016-12-20
Formatting changes for RISC-V
Andrew Waterman
2016-11-01
Add support for RISC-V architecture.
Nick Clifton