diff options
| author | Andrew Waterman <andrew@sifive.com> | 2017-05-15 08:50:57 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-06-23 09:23:58 -0700 |
| commit | 9bdfdbf929d581cf845ffc815ae94a39d9f7b032 (patch) | |
| tree | 93e5c4b5b4e64ffc1a26b053b959c4c9acef0968 /opcodes/riscv-opc.c | |
| parent | 94f78a777c396fa1ce2f40d34afed1b6b5012196 (diff) | |
RISC-V: Fix SLTI disassembly
2017-06-23 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
alias; do not mark SLTI instruction as an alias.
Diffstat (limited to 'opcodes/riscv-opc.c')
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 0188a653f2..9914c44744 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -245,9 +245,9 @@ const struct riscv_opcode riscv_opcodes[] = {"snez", "I", "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS }, {"sltz", "I", "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS }, {"sgtz", "I", "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS }, -{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS }, +{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 }, {"slt", "I", "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 }, -{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 }, +{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS }, {"sltiu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 }, {"sltu", "I", "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 }, {"sltu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS }, |