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path: root/opcodes/i386-dis.c
AgeCommit message (Expand)Author
2018-01-03Update year range in copyright notice of binutils filesAlan Modra
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich
2017-11-23x86: correct UDnJan Beulich
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich
2017-11-15x86: use correct register namesJan Beulich
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu
2017-07-18Fix spelling typos.Yuri Chornovian
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu
2017-06-15i386-dis: Check valid bnd registerH.J. Lu
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu
2017-03-06Add support for Intel CET instructionsH.J. Lu
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich
2017-02-24x86: also correctly support TEST opcode aliasesJan Beulich
2017-02-23x86: drop stray VEX opcode 82 referencesJan Beulich
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist
2017-01-02Update year range in copyright notice of all files.Alan Modra
2016-12-01Fix abort in x86 disassembler.Nick Clifton
2016-11-28X86: Ignore REX_B bit for 32-bit XOP instructionsAmit Pawar
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu
2016-11-08X86: Remove the THREE_BYTE_0F7A entryH.J. Lu
2016-11-07X86: Properly handle bad FPU opcodeH.J. Lu
2016-11-03X86: Reuse opcode 0x80 decoder for opcode 0x82H.J. Lu
2016-11-03X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu
2016-11-03X86: Rename REG_82 to REG_83H.J. Lu
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist
2016-10-21X86: Remove pcommit instructionH.J. Lu
2016-10-20Check invalid mask registersH.J. Lu
2016-10-18Check addr32flag instead of sizeflag for rip/eipH.J. Lu
2016-10-18Remove the remaining SSE5 supportH.J. Lu
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra
2016-09-30Don't assign alt twiceH.J. Lu
2016-08-24X86: Add ptwrite instructionH.J. Lu
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu
2016-05-10Enable Intel RDPID instruction.Alexander Fomin
2016-04-23Skip if size of bfd_vma is smaller than address sizeH.J. Lu
2016-02-15Add parentheses to prevent truncated addressesH.J. Lu
2016-01-01Copyright update for binutilsAlan Modra
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