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AgeCommit message (Expand)Author
2018-01-03Update year range in copyright notice of binutils filesAlan Modra
2018-01-03ChangeLog rotationAlan Modra
2018-01-02x86: partial revert of 10c17abdd0Jan Beulich
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson
2017-12-19Correct disassembly of dot product instructions.Tamar Christina
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich
2017-12-18x86: drop FloatReg and FloatAccJan Beulich
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich
2017-12-15Fix disassembly for PowerPCDimitar Dimitrov
2017-12-15x86: drop stray CheckRegSize usesJan Beulich
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson
2017-12-13This patch enables disassembler_needs_relocs for PRU. It is needed to print c...Dimitar Dimitrov
2017-12-11[Binutils][Objdump]Check symbol section information while search a mapping sy...Renlin Li
2017-12-03Fix "FAIL: VLE relocations 3"Alan Modra
2017-12-01Use consistent types for holding instructions, instruction masks, etc.Peter Bergner
2017-11-30x86: derive DispN from BaseIndexJan Beulich
2017-11-30x86: drop Vec_Disp8Jan Beulich
2017-11-29Support --localedir, --datarootdir and --datadirStefan Stroe
2017-11-27Update the simplified Chinese translation of the messages in the opcodes libr...Nick Clifton
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich
2017-11-23x86: correct UDnJan Beulich
2017-11-22Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.Igor Tsimbalist
2017-11-22Update ChangeLogIgor Tsimbalist
2017-11-22Remove Vec_Disp8 from vpcompressb and vpexpandb.Igor Tsimbalist
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina
2017-11-16Correct AArch64 crypto dependencies.Tamar Christina
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich
2017-11-15x86: use correct register namesJan Beulich
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich
2017-11-14x86: string insns don't allow displacementsJan Beulich
2017-11-13x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffixJan Beulich
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina
2017-11-09Add the operand encoding types for the new Armv8.2-a back-ported instructions...Tamar Christina
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang
2017-11-07opcodes/arc: Fix incorrect insn_class for some nps insnsAndrew Burgess
2017-11-07ngettext supportAlan Modra
2017-11-03[ARC] Force the disassam to use the hexadecimal number for printingclaziss