summaryrefslogtreecommitdiff
path: root/drivers/clk/uniphier/clk-uniphier-core.c
blob: 9a7d03aa59718089af94d0992bda04b865c33959 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
/*
 * Copyright (C) 2016-2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>

#include "clk-uniphier.h"

/**
 * struct uniphier_clk_priv - private data for UniPhier clock driver
 *
 * @base: base address of the clock provider
 * @data: SoC specific data
 */
struct uniphier_clk_priv {
	struct udevice *dev;
	void __iomem *base;
	const struct uniphier_clk_data *data;
};

static void uniphier_clk_gate_enable(struct uniphier_clk_priv *priv,
				     const struct uniphier_clk_gate_data *gate)
{
	u32 val;

	val = readl(priv->base + gate->reg);
	val |= BIT(gate->bit);
	writel(val, priv->base + gate->reg);
}

static void uniphier_clk_mux_set_parent(struct uniphier_clk_priv *priv,
					const struct uniphier_clk_mux_data *mux,
					u8 id)
{
	u32 val;
	int i;

	for (i = 0; i < mux->num_parents; i++) {
		if (mux->parent_ids[i] != id)
			continue;

		val = readl(priv->base + mux->reg);
		val &= ~mux->masks[i];
		val |= mux->vals[i];
		writel(val, priv->base + mux->reg);
		return;
	}

	WARN_ON(1);
}

static u8 uniphier_clk_mux_get_parent(struct uniphier_clk_priv *priv,
				      const struct uniphier_clk_mux_data *mux)
{
	u32 val;
	int i;

	val = readl(priv->base + mux->reg);

	for (i = 0; i < mux->num_parents; i++)
		if ((mux->masks[i] & val) == mux->vals[i])
			return mux->parent_ids[i];

	dev_err(priv->dev, "invalid mux setting\n");

	return UNIPHIER_CLK_ID_INVALID;
}

static const struct uniphier_clk_data *uniphier_clk_get_data(
					struct uniphier_clk_priv *priv, u8 id)
{
	const struct uniphier_clk_data *data;

	for (data = priv->data; data->type != UNIPHIER_CLK_TYPE_END; data++)
		if (data->id == id)
			return data;

	dev_err(priv->dev, "id=%u not found\n", id);

	return NULL;
}

static const struct uniphier_clk_data *uniphier_clk_get_parent_data(
					struct uniphier_clk_priv *priv,
					const struct uniphier_clk_data *data)
{
	const struct uniphier_clk_data *parent_data;
	u8 parent_id = UNIPHIER_CLK_ID_INVALID;

	switch (data->type) {
	case UNIPHIER_CLK_TYPE_GATE:
		parent_id = data->data.gate.parent_id;
		break;
	case UNIPHIER_CLK_TYPE_MUX:
		parent_id = uniphier_clk_mux_get_parent(priv, &data->data.mux);
		break;
	default:
		break;
	}

	if (parent_id == UNIPHIER_CLK_ID_INVALID)
		return NULL;

	parent_data = uniphier_clk_get_data(priv, parent_id);

	WARN_ON(!parent_data);

	return parent_data;
}

static void __uniphier_clk_enable(struct uniphier_clk_priv *priv,
				  const struct uniphier_clk_data *data)
{
	const struct uniphier_clk_data *parent_data;

	if (data->type == UNIPHIER_CLK_TYPE_GATE)
		uniphier_clk_gate_enable(priv, &data->data.gate);

	parent_data = uniphier_clk_get_parent_data(priv, data);
	if (!parent_data)
		return;

	return __uniphier_clk_enable(priv, parent_data);
}

static int uniphier_clk_enable(struct clk *clk)
{
	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
	const struct uniphier_clk_data *data;

	data = uniphier_clk_get_data(priv, clk->id);
	if (!data)
		return -ENODEV;

	__uniphier_clk_enable(priv, data);

	return 0;
}

static unsigned long __uniphier_clk_get_rate(
					struct uniphier_clk_priv *priv,
					const struct uniphier_clk_data *data)
{
	const struct uniphier_clk_data *parent_data;

	if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
		return data->data.rate.fixed_rate;

	parent_data = uniphier_clk_get_parent_data(priv, data);
	if (!parent_data)
		return 0;

	return __uniphier_clk_get_rate(priv, parent_data);
}

static unsigned long uniphier_clk_get_rate(struct clk *clk)
{
	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
	const struct uniphier_clk_data *data;

	data = uniphier_clk_get_data(priv, clk->id);
	if (!data)
		return -ENODEV;

	return __uniphier_clk_get_rate(priv, data);
}

static unsigned long __uniphier_clk_set_rate(
					struct uniphier_clk_priv *priv,
					const struct uniphier_clk_data *data,
					unsigned long rate, bool set)
{
	const struct uniphier_clk_data *best_parent_data = NULL;
	const struct uniphier_clk_data *parent_data;
	unsigned long best_rate = 0;
	unsigned long parent_rate;
	u8 parent_id;
	int i;

	if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
		return data->data.rate.fixed_rate;

	if (data->type == UNIPHIER_CLK_TYPE_GATE) {
		parent_data = uniphier_clk_get_parent_data(priv, data);
		if (!parent_data)
			return 0;

		return __uniphier_clk_set_rate(priv, parent_data, rate, set);
	}

	if (WARN_ON(data->type != UNIPHIER_CLK_TYPE_MUX))
		return -EINVAL;

	for (i = 0; i < data->data.mux.num_parents; i++) {
		parent_id = data->data.mux.parent_ids[i];
		parent_data = uniphier_clk_get_data(priv, parent_id);
		if (WARN_ON(!parent_data))
			return -EINVAL;

		parent_rate = __uniphier_clk_set_rate(priv, parent_data, rate,
						      false);

		if (parent_rate <= rate && best_rate < parent_rate) {
			best_rate = parent_rate;
			best_parent_data = parent_data;
		}
	}

	dev_dbg(priv->dev, "id=%u, best_rate=%lu\n", data->id, best_rate);

	if (!best_parent_data)
		return -EINVAL;

	if (!set)
		return best_rate;

	uniphier_clk_mux_set_parent(priv, &data->data.mux,
				    best_parent_data->id);

	return best_rate = __uniphier_clk_set_rate(priv, best_parent_data,
						   rate, true);
}

static unsigned long uniphier_clk_set_rate(struct clk *clk, ulong rate)
{
	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
	const struct uniphier_clk_data *data;

	data = uniphier_clk_get_data(priv, clk->id);
	if (!data)
		return -ENODEV;

	return __uniphier_clk_set_rate(priv, data, rate, true);
}

static const struct clk_ops uniphier_clk_ops = {
	.enable = uniphier_clk_enable,
	.get_rate = uniphier_clk_get_rate,
	.set_rate = uniphier_clk_set_rate,
};

static int uniphier_clk_probe(struct udevice *dev)
{
	struct uniphier_clk_priv *priv = dev_get_priv(dev);
	fdt_addr_t addr;

	addr = devfdt_get_addr(dev->parent);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->base = devm_ioremap(dev, addr, SZ_4K);
	if (!priv->base)
		return -ENOMEM;

	priv->dev = dev;
	priv->data = (void *)dev_get_driver_data(dev);

	return 0;
}

static const struct udevice_id uniphier_clk_match[] = {
	/* System clock */
	{
		.compatible = "socionext,uniphier-ld4-clock",
		.data = (ulong)uniphier_pxs2_sys_clk_data,
	},
	{
		.compatible = "socionext,uniphier-pro4-clock",
		.data = (ulong)uniphier_pxs2_sys_clk_data,
	},
	{
		.compatible = "socionext,uniphier-sld8-clock",
		.data = (ulong)uniphier_pxs2_sys_clk_data,
	},
	{
		.compatible = "socionext,uniphier-pro5-clock",
		.data = (ulong)uniphier_pxs2_sys_clk_data,
	},
	{
		.compatible = "socionext,uniphier-pxs2-clock",
		.data = (ulong)uniphier_pxs2_sys_clk_data,
	},
	{
		.compatible = "socionext,uniphier-ld11-clock",
		.data = (ulong)uniphier_ld20_sys_clk_data,
	},
	{
		.compatible = "socionext,uniphier-ld20-clock",
		.data = (ulong)uniphier_ld20_sys_clk_data,
	},
	{
		.compatible = "socionext,uniphier-pxs3-clock",
		.data = (ulong)uniphier_pxs3_sys_clk_data,
	},
	/* Media I/O clock */
	{
		.compatible = "socionext,uniphier-ld4-mio-clock",
		.data = (ulong)uniphier_mio_clk_data,
	},
	{
		.compatible = "socionext,uniphier-pro4-mio-clock",
		.data = (ulong)uniphier_mio_clk_data,
	},
	{
		.compatible = "socionext,uniphier-sld8-mio-clock",
		.data = (ulong)uniphier_mio_clk_data,
	},
	{
		.compatible = "socionext,uniphier-pro5-sd-clock",
		.data = (ulong)uniphier_mio_clk_data,
	},
	{
		.compatible = "socionext,uniphier-pxs2-sd-clock",
		.data = (ulong)uniphier_mio_clk_data,
	},
	{
		.compatible = "socionext,uniphier-ld11-mio-clock",
		.data = (ulong)uniphier_mio_clk_data,
	},
	{
		.compatible = "socionext,uniphier-ld20-sd-clock",
		.data = (ulong)uniphier_mio_clk_data,
	},
	{
		.compatible = "socionext,uniphier-pxs3-sd-clock",
		.data = (ulong)uniphier_mio_clk_data,
	},
	{ /* sentinel */ }
};

U_BOOT_DRIVER(uniphier_clk) = {
	.name = "uniphier-clk",
	.id = UCLASS_CLK,
	.of_match = uniphier_clk_match,
	.probe = uniphier_clk_probe,
	.priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
	.ops = &uniphier_clk_ops,
};