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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/dts/rk3288-miniarm.dtsi12
-rw-r--r--arch/arm/dts/rk3399-evb.dts1
-rw-r--r--arch/arm/include/asm/arch-rockchip/boot_mode.h19
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_rk3399.h4
-rw-r--r--arch/arm/include/asm/arch-rockchip/pwm.h2
-rw-r--r--arch/arm/mach-rockchip/Kconfig3
-rw-r--r--arch/arm/mach-rockchip/Makefile3
-rw-r--r--arch/arm/mach-rockchip/rk3036-board.c122
-rw-r--r--arch/arm/mach-rockchip/rk3288-board-spl.c5
-rw-r--r--arch/arm/mach-rockchip/rk3288-board.c (renamed from arch/arm/mach-rockchip/board.c)50
-rw-r--r--arch/arm/mach-rockchip/rk3288/sdram_rk3288.c7
12 files changed, 205 insertions, 25 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 634bc48413..f55d5b2cd7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -851,6 +851,8 @@ config ARCH_ROCKCHIP
select DM_SPI
select DM_SPI_FLASH
select DM_USB if USB
+ select DM_PWM
+ select DM_REGULATOR
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi
index b88987557a..ceb4e2bdb1 100644
--- a/arch/arm/dts/rk3288-miniarm.dtsi
+++ b/arch/arm/dts/rk3288-miniarm.dtsi
@@ -116,18 +116,6 @@
cpu0-supply = <&vdd_cpu>;
};
-&emmc {
- broken-cd;
- bus-width = <8>;
- cap-mmc-highspeed;
- disable-wp;
- non-removable;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
- status = "okay";
-};
-
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index bd7801b9a5..fa60e191ed 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -23,6 +23,7 @@
regulator-name = "vdd_center";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
+ regulator-init-microvolt = <950000>;
regulator-always-on;
regulator-boot-on;
status = "okay";
diff --git a/arch/arm/include/asm/arch-rockchip/boot_mode.h b/arch/arm/include/asm/arch-rockchip/boot_mode.h
new file mode 100644
index 0000000000..bd65f60bf2
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/boot_mode.h
@@ -0,0 +1,19 @@
+#ifndef __REBOOT_MODE_H
+#define __REBOOT_MODE_H
+
+/* high 24 bits is tag, low 8 bits is type */
+#define REBOOT_FLAG 0x5242C300
+/* normal boot */
+#define BOOT_NORMAL (REBOOT_FLAG + 0)
+/* enter loader rockusb mode */
+#define BOOT_LOADER (REBOOT_FLAG + 1)
+/* enter recovery */
+#define BOOT_RECOVERY (REBOOT_FLAG + 3)
+/* enter fastboot mode */
+#define BOOT_FASTBOOT (REBOOT_FLAG + 9)
+/* enter charging mode */
+#define BOOT_CHARGING (REBOOT_FLAG + 11)
+/* enter usb mass storage mode */
+#define BOOT_UMS (REBOOT_FLAG + 12)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
index c919f47745..6776e484b7 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -64,9 +64,9 @@ check_member(rk3399_cru, sdio1_con[1], 0x594);
#define APLL_HZ (600*MHz)
#define GPLL_HZ (594*MHz)
#define CPLL_HZ (384*MHz)
-#define PPLL_HZ (594*MHz)
+#define PPLL_HZ (676*MHz)
-#define PMU_PCLK_HZ (99*MHz)
+#define PMU_PCLK_HZ (48*MHz)
#define ACLKM_CORE_HZ (300*MHz)
#define ATCLK_CORE_HZ (300*MHz)
diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h
index 08ff94591c..5d9a178a70 100644
--- a/arch/arm/include/asm/arch-rockchip/pwm.h
+++ b/arch/arm/include/asm/arch-rockchip/pwm.h
@@ -10,8 +10,8 @@
struct rk3288_pwm {
u32 cnt;
- u32 period_hpr;
u32 duty_lpr;
+ u32 period_hpr;
u32 ctrl;
};
check_member(rk3288_pwm, ctrl, 0xc);
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 1aac3c85ba..8a5d62a735 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -42,6 +42,9 @@ config ROCKCHIP_SPL_BACK_TO_BROM
SPL will return to the boot rom, which will then load the U-Boot
binary to keep going on.
+config SPL_MMC_SUPPORT
+ default y if !ROCKCHIP_SPL_BACK_TO_BROM
+
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 157d42fe96..6e79fed485 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -9,7 +9,8 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
obj-$(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) += save_boot_param.o
else
-obj-$(CONFIG_ROCKCHIP_RK3288) += board.o
+obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
+obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
endif
ifndef CONFIG_ARM64
obj-y += rk_timer.o
diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c
new file mode 100644
index 0000000000..bf2b268f8b
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3036-board.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/grf_rk3036.h>
+#include <asm/arch/boot_mode.h>
+#include <asm/arch/sdram_rk3036.h>
+#include <asm/gpio.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GRF_BASE 0x20008000
+
+static void setup_boot_mode(void)
+{
+ struct rk3036_grf *const grf = (void *)GRF_BASE;
+ int boot_mode = readl(&grf->os_reg[4]);
+
+ debug("boot mode %x.\n", boot_mode);
+
+ /* Clear boot mode */
+ writel(BOOT_NORMAL, &grf->os_reg[4]);
+
+ switch (boot_mode) {
+ case BOOT_FASTBOOT:
+ printf("enter fastboot!\n");
+ setenv("preboot", "setenv preboot; fastboot usb0");
+ break;
+ case BOOT_UMS:
+ printf("enter UMS!\n");
+ setenv("preboot", "setenv preboot; ums mmc 0");
+ break;
+ }
+}
+
+__weak int rk_board_late_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_boot_mode();
+
+ return rk_board_late_init();
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = sdram_size();
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3036_otg_data = {
+ .rx_fifo_sz = 512,
+ .np_tx_fifo_sz = 16,
+ .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node;
+ const char *mode;
+ bool matched = false;
+ const void *blob = gd->fdt_blob;
+
+ /* find the usb_otg node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "rockchip,rk3288-usb");
+
+ while (node > 0) {
+ mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ if (mode && strcmp(mode, "otg") == 0) {
+ matched = true;
+ break;
+ }
+
+ node = fdt_node_offset_by_compatible(blob, node,
+ "rockchip,rk3288-usb");
+ }
+ if (!matched) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+ rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+ return dwc2_udc_probe(&rk3036_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index ae509ffab2..0f40351769 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -206,7 +206,7 @@ void board_init_f(ulong dummy)
debug("DRAM init failed: %d\n", ret);
return;
}
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
#endif
}
@@ -273,6 +273,9 @@ void spl_board_init(void)
}
preloader_console_init();
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+ back_to_bootrom();
+#endif
return;
err:
printf("spl_board_init: Error %d\n", ret);
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 6c36bf9397..baf9522bcd 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -8,25 +8,65 @@
#include <clk.h>
#include <dm.h>
#include <ram.h>
+#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
+#include <asm/arch/pmu_rk3288.h>
+#include <asm/arch/boot_mode.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
DECLARE_GLOBAL_DATA_PTR;
+#define PMU_BASE 0xff730000
+
+static void setup_boot_mode(void)
+{
+ struct rk3288_pmu *const pmu = (void *)PMU_BASE;
+ int boot_mode = readl(&pmu->sys_reg[0]);
+
+ debug("boot mode %x.\n", boot_mode);
+
+ /* Clear boot mode */
+ writel(BOOT_NORMAL, &pmu->sys_reg[0]);
+
+ switch (boot_mode) {
+ case BOOT_FASTBOOT:
+ printf("enter fastboot!\n");
+ setenv("preboot", "setenv preboot; fastboot usb0");
+ break;
+ case BOOT_UMS:
+ printf("enter UMS!\n");
+ setenv("preboot", "setenv preboot; if mmc dev 0;"
+ "then ums mmc 0; else ums mmc 1;fi");
+ break;
+ }
+}
+
+__weak int rk_board_late_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_boot_mode();
+
+ return rk_board_late_init();
+}
+
int board_init(void)
{
#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
struct udevice *pinctrl;
int ret;
- /*
- * We need to implement sdcard iomux here for the further
- * initlization, otherwise, it'll hit sdcard command sending
- * timeout exception.
- */
+ /*
+ * We need to implement sdcard iomux here for the further
+ * initlization, otherwise, it'll hit sdcard command sending
+ * timeout exception.
+ */
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("%s: Cannot find pinctrl device\n", __func__);
diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index cf9ef2e845..8020e9c6e2 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -755,10 +755,11 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
}
/*
- * we use the 0x00000000~0xfeffffff space since 0xff000000~0xffffffff
- * is SoC register space (i.e. reserved)
+ * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
+ * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
+ * inaccessible for some IP controller.
*/
- size_mb = min(size_mb, 0xff000000 >> 20);
+ size_mb = min(size_mb, 0xfe000000 >> 20);
return size_mb;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 10:27:48 +0000