diff options
80 files changed, 549 insertions, 1127 deletions
@@ -14,6 +14,12 @@ source "arch/Kconfig" menu "General setup" +config BROKEN + bool + help + This option cannot be enabled. It is used as dependency + for broken and incomplete features. + config LOCALVERSION string "Local version - append to U-Boot release" help diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 64e0ee43f1..83b7aa51dc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -698,6 +698,7 @@ config ARCH_SUNXI select SPL_SYS_MALLOC_SIMPLE if SPL select SYS_NS16550 select SPL_SYS_THUMB_BUILD if !ARM64 + select SYS_THUMB_BUILD if !ARM64 select USB if DISTRO_DEFAULTS select USB_STORAGE if DISTRO_DEFAULTS select USB_KEYBOARD if DISTRO_DEFAULTS diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5b90280468..6db64f9101 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -309,6 +309,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \ sun8i-a33-olinuxino.dtb \ sun8i-a33-q8-tablet.dtb \ sun8i-a33-sinlinx-sina33.dtb \ + sun8i-r16-bananapi-m2m.dtb \ sun8i-r16-nintendo-nes-classic-edition.dtb \ sun8i-r16-parrot.dtb dtb-$(CONFIG_MACH_SUN8I_A83T) += \ diff --git a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts new file mode 100644 index 0000000000..eaf0966672 --- /dev/null +++ b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2017 Free Electrons <maxime.ripard@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BananaPi M2 Magic"; + compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "bpi-m2m:blue:usr"; + gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; + }; + + green { + label = "bpi-m2m:green:usr"; + gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; + }; + + red { + label = "bpi-m2m:red:power"; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ + }; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&cpu0_opp_table { + opp@1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; +}; + +&dai { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +/* This is the i2c bus exposed on the DSI connector for the touch panel */ +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "disabled"; +}; + +/* This is the i2c bus exposed on the GPIO header */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "disabled"; +}; + +/* This is the i2c bus exposed on the CSI connector to control the sensor */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp223.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +/* + * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same + * time, with the two being in sync. Since this is not really + * supported right now, just use the two as always on, and we will fix + * it later. + */ +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi0"; +}; + +®_dldo2 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi1"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&sound { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index 5adfd9bca2..72e95afd78 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -1,5 +1,14 @@ #include <config.h> +/* + * This is the maximum size the U-Boot binary can be, which is basically + * the start of the environment, minus the start of the U-Boot binary in + * the MMC. This makes the assumption that the MMC is using 512-bytes + * blocks, but devices using something other than that remains to be + * seen. + */ +#define UBOOT_MMC_MAX_SIZE (CONFIG_ENV_OFFSET - (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)) + / { binman { filename = "u-boot-sunxi-with-spl.bin"; @@ -8,6 +17,9 @@ filename = "spl/sunxi-spl.bin"; }; u-boot-img { +#ifdef CONFIG_MMC + size = <UBOOT_MMC_MAX_SIZE>; +#endif pos = <CONFIG_SPL_PAD_TO>; }; }; diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h index 5dfcbf3b01..b4ea2f8cfb 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -158,7 +158,7 @@ struct sunxi_ccm_reg { #define CPU_CLK_SRC_OSC24M 0 #define CPU_CLK_SRC_PLL1 1 -#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0xff) << 8) +#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8) #define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16) #define CCM_PLL1_CTRL_EN (0x1 << 31) #define CMM_PLL1_CLOCK_TIME_2 (0x2 << 24) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c869ae2548..98c56ad7dc 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -402,15 +402,6 @@ config FSP_BROKEN_HOB do not overwrite the important boot service data which is used by FSP, otherwise the subsequent call to fsp_notify() will fail. -config FSP_LOCKDOWN_SPI - bool - depends on HAVE_FSP - help - Some Intel FSP (like Braswell) does SPI lock-down during the call - to fsp_notify(INIT_PHASE_BOOT). This option should be turned on - for such FSP and U-Boot will configure the SPI opcode registers - before the lock-down. - config ENABLE_MRC_CACHE bool "Enable MRC cache" depends on !EFI && !SYS_COREBOOT @@ -664,6 +655,7 @@ endmenu config HAVE_ACPI_RESUME bool "Enable ACPI S3 resume" + select ENABLE_MRC_CACHE help Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping state where all system context is lost except system memory. U-Boot diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig index 0e214a7432..31ac279c56 100644 --- a/arch/x86/cpu/braswell/Kconfig +++ b/arch/x86/cpu/braswell/Kconfig @@ -12,7 +12,6 @@ config INTEL_BRASWELL imply HAVE_INTEL_ME imply HAVE_VBT imply ENABLE_MRC_CACHE - imply ENV_IS_IN_SPI_FLASH imply AHCI_PCI imply ICH_SPI imply MMC @@ -32,8 +31,4 @@ config FSP_ADDR hex default 0xfff20000 -config FSP_LOCKDOWN_SPI - bool - default y - endif diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile index ddf6d2804a..4a639b83f5 100644 --- a/arch/x86/cpu/braswell/Makefile +++ b/arch/x86/cpu/braswell/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += braswell.o cpu.o early_uart.o fsp_configs.o +obj-y += braswell.o early_uart.o fsp_configs.o diff --git a/arch/x86/cpu/braswell/cpu.c b/arch/x86/cpu/braswell/cpu.c deleted file mode 100644 index 6ff9036597..0000000000 --- a/arch/x86/cpu/braswell/cpu.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Derived from arch/x86/cpu/baytrail/cpu.c - */ - -#include <common.h> -#include <cpu.h> -#include <dm.h> -#include <asm/cpu.h> -#include <asm/cpu_x86.h> -#include <asm/io.h> -#include <asm/lapic.h> -#include <asm/msr.h> -#include <asm/turbo.h> - -static const unsigned int braswell_bus_freq_table[] = { - 83333333, - 100000000, - 133333333, - 116666666, - 80000000, - 93333333, - 90000000, - 88900000, - 87500000 -}; - -static unsigned int braswell_bus_freq(void) -{ - msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL); - - if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table))) - return braswell_bus_freq_table[clk_info.lo & 0xf]; - - return 0; -} - -static unsigned long braswell_tsc_freq(void) -{ - msr_t platform_info; - ulong bclk = braswell_bus_freq(); - - if (!bclk) - return 0; - - platform_info = msr_read(MSR_PLATFORM_INFO); - - return bclk * ((platform_info.lo >> 8) & 0xff); -} - -static int braswell_get_info(struct udevice *dev, struct cpu_info *info) -{ - info->cpu_freq = braswell_tsc_freq(); - info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU); - - return 0; -} - -static int braswell_get_count(struct udevice *dev) -{ - int ecx = 0; - - /* - * Use the algorithm described in Intel 64 and IA-32 Architectures - * Software Developer's Manual Volume 3 (3A, 3B & 3C): System - * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping - * of CPUID Extended Topology Leaf. - */ - while (1) { - struct cpuid_result leaf_b; - - leaf_b = cpuid_ext(0xb, ecx); - - /* - * Braswell doesn't have hyperthreading so just determine the - * number of cores by from level type (ecx[15:8] == * 2) - */ - if ((leaf_b.ecx & 0xff00) == 0x0200) - return leaf_b.ebx & 0xffff; - - ecx++; - } - - return 0; -} - -static void braswell_set_max_freq(void) -{ - msr_t perf_ctl; - msr_t msr; - - /* Enable speed step */ - msr = msr_read(MSR_IA32_MISC_ENABLES); - msr.lo |= (1 << 16); - msr_write(MSR_IA32_MISC_ENABLES, msr); - - /* Enable Burst Mode */ - msr = msr_read(MSR_IA32_MISC_ENABLES); - msr.hi = 0; - msr_write(MSR_IA32_MISC_ENABLES, msr); - - /* - * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to - * bits [15:8] of the PERF_CTL - */ - msr = msr_read(MSR_IACORE_TURBO_RATIOS); - perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; - - /* - * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to - * bits [7:0] of the PERF_CTL - */ - msr = msr_read(MSR_IACORE_TURBO_VIDS); - perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; - - perf_ctl.hi = 0; - msr_write(MSR_IA32_PERF_CTL, perf_ctl); -} - -static int braswell_probe(struct udevice *dev) -{ - debug("Init Braswell core\n"); - - /* - * On Braswell the turbo disable bit is actually scoped at the - * building-block level, not package. For non-BSP cores that are - * within a building block, enable turbo. The cores within the BSP's - * building block will just see it already enabled and move on. - */ - if (lapicid()) - turbo_enable(); - - /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ - msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008), - msr_clrsetbits_64(MSR_POWER_MISC, - ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0); - - /* Disable C1E */ - msr_clrsetbits_64(MSR_POWER_CTL, 2, 0); - msr_setbits_64(MSR_POWER_MISC, 0x44); - - /* Set this core to max frequency ratio */ - braswell_set_max_freq(); - - return 0; -} - -static const struct udevice_id braswell_ids[] = { - { .compatible = "intel,braswell-cpu" }, - { } -}; - -static const struct cpu_ops braswell_ops = { - .get_desc = cpu_x86_get_desc, - .get_info = braswell_get_info, - .get_count = braswell_get_count, - .get_vendor = cpu_x86_get_vendor, -}; - -U_BOOT_DRIVER(cpu_x86_braswell_drv) = { - .name = "cpu_x86_braswell", - .id = UCLASS_CPU, - .of_match = braswell_ids, - .bind = cpu_x86_bind, - .probe = braswell_probe, - .ops = &braswell_ops, -}; diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts index 1ccb605991..41e72f3eb6 100644 --- a/arch/x86/dts/cherryhill.dts +++ b/arch/x86/dts/cherryhill.dts @@ -37,28 +37,28 @@ cpu@0 { device_type = "cpu"; - compatible = "intel,braswell-cpu"; + compatible = "cpu-x86"; reg = <0>; intel,apic-id = <0>; }; cpu@1 { device_type = "cpu"; - compatible = "intel,braswell-cpu"; + compatible = "cpu-x86"; reg = <1>; intel,apic-id = <2>; }; cpu@2 { device_type = "cpu"; - compatible = "intel,braswell-cpu"; + compatible = "cpu-x86"; reg = <2>; intel,apic-id = <4>; }; cpu@3 { device_type = "cpu"; - compatible = "intel,braswell-cpu"; + compatible = "cpu-x86"; reg = <3>; intel,apic-id = <6>; }; @@ -143,6 +143,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich9-spi"; + intel,spi-lock-down; spi-flash@0 { #address-cells = <1>; @@ -194,7 +195,6 @@ fsp,pmic-i2c-bus = <0>; fsp,enable-isp; fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>; - fsp,turbo-mode; fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>; fsp,sd-detect-chk; }; diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/acpi/sleepstates.asl index 5600723084..5600723084 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl +++ b/arch/x86/include/asm/acpi/sleepstates.asl diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl index a80d2c0e51..cf3de7cde4 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl @@ -36,4 +36,4 @@ Scope (\_SB) } /* Chipset specific sleep states */ -#include "sleepstates.asl" +#include <asm/acpi/sleepstates.asl> diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl index 1ecf153c0f..db59c460e3 100644 --- a/arch/x86/include/asm/arch-quark/acpi/platform.asl +++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl @@ -33,4 +33,4 @@ Scope (\_SB) } /* Chipset specific sleep states */ -#include "sleepstates.asl" +#include <asm/acpi/sleepstates.asl> diff --git a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl deleted file mode 100644 index 63c82fa123..0000000000 --- a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) -Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) -Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) -Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 1714d13228..3397bb83ea 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -19,8 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern void ich_spi_config_opcode(struct udevice *dev); - int checkcpu(void) { return 0; @@ -51,28 +49,6 @@ void board_final_cleanup(void) { u32 status; -#ifdef CONFIG_FSP_LOCKDOWN_SPI - struct udevice *dev; - - /* - * Some Intel FSP (like Braswell) does SPI lock-down during the call - * to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done, - * it's bootloader's responsibility to configure the SPI controller's - * opcode registers properly otherwise SPI controller driver doesn't - * know how to communicate with the SPI flash device. - * - * Note we cannot do such configuration elsewhere (eg: during the SPI - * controller driver's probe() routine), because: - * - * 1). U-Boot SPI controller driver does not set the lock-down bit - * 2). Any SPI transfer will corrupt the contents of these registers - * - * Hence we have to do it right here before SPI lock-down bit is set. - */ - if (!uclass_first_device_err(UCLASS_SPI, &dev)) - ich_spi_config_opcode(dev); -#endif - /* call into FspNotify */ debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); status = fsp_notify(NULL, INIT_PHASE_BOOT); diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index a19b067f8f..af7127691f 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -37,6 +37,10 @@ static int save_vesa_mode(struct vesa_mode_info *vesa) /* * If there is no graphics info structure, bail out and keep * running on the serial console. + * + * Note: on some platforms (eg: Braswell), the FSP will not produce + * the graphics info HOB unless you plug some cables to the display + * interface (eg: HDMI) on the board. */ if (!ginfo) { debug("FSP graphics hand-off block not found\n"); diff --git a/board/ti/sdp4430/cmd_bat.c b/board/ti/sdp4430/cmd_bat.c index 7e8dbb1b00..4c7beeb3ef 100644 --- a/board/ti/sdp4430/cmd_bat.c +++ b/board/ti/sdp4430/cmd_bat.c @@ -39,4 +39,4 @@ U_BOOT_CMD( "bat startcharge - start charging via USB\n" "bat stopcharge - stop charging\n" ); -#endif /* CONFIG_BAT_CMD */ +#endif /* CONFIG_CMD_BAT */ diff --git a/cmd/fastboot/Kconfig b/cmd/fastboot/Kconfig index 214bbc23fc..4ce7a775e2 100644 --- a/cmd/fastboot/Kconfig +++ b/cmd/fastboot/Kconfig @@ -81,6 +81,16 @@ config FASTBOOT_FLASH_MMC_DEV regarding the non-volatile storage device. Define this to the eMMC device that fastboot should use to store the image. +config FASTBOOT_FLASH_NAND_DEV + int "Define FASTBOOT NAND FLASH default device" + depends on FASTBOOT_FLASH && NAND + depends on CMD_MTDPARTS + default 0 if ARCH_SUNXI && NAND_SUNXI + help + The fastboot "flash" command requires additional information + regarding the non-volatile storage device. Define this to + the NAND device that fastboot should use to store the image. + config FASTBOOT_GPT_NAME string "Target name for updating GPT" depends on FASTBOOT_FLASH @@ -282,14 +282,14 @@ static int create_gpt_partitions_list(int numparts, const char *guid, strcat(partitions_list, "name="); strncat(partitions_list, (const char *)curr->gpt_part_info.name, PART_NAME_LEN + 1); - strcat(partitions_list, ",start="); - prettyprint_part_size(partstr, (unsigned long)curr->gpt_part_info.start, - (unsigned long) curr->gpt_part_info.blksz); + sprintf(partstr, ",start=0x%llx", + (unsigned long long)curr->gpt_part_info.start * + curr->gpt_part_info.blksz); /* one extra byte for NULL */ strncat(partitions_list, partstr, PART_NAME_LEN + 1); - strcat(partitions_list, ",size="); - prettyprint_part_size(partstr, curr->gpt_part_info.size, - curr->gpt_part_info.blksz); + sprintf(partstr, ",size=0x%llx", + (unsigned long long)curr->gpt_part_info.size * + curr->gpt_part_info.blksz); strncat(partitions_list, partstr, PART_NAME_LEN + 1); strcat(partitions_list, ",uuid="); diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig new file mode 100644 index 0000000000..82cd2c440b --- /dev/null +++ b/configs/Bananapi_m2m_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_CONS_INDEX=1 +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=600 +CONFIG_DRAM_ZQ=15291 +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="PB4" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_USB0_ID_DET="PH8" +CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-bananapi-m2m" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_PARTITION_UUIDS is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index d94b634a44..06f2b9dae4 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y CONFIG_BOOTDELAY=1 CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb" CONFIG_SPL=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index c1849e38bb..f91890c744 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -6,8 +6,6 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_ACPI_TABLE=y CONFIG_FIT=y -CONFIG_BOOTSTAGE=y -CONFIG_BOOTSTAGE_REPORT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -25,7 +23,6 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 5918e729d1..e5fea42fa6 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index 1a16ed1ad6..5792e7a4a3 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881979 diff --git a/disk/part_efi.c b/disk/part_efi.c index 782f8be502..7862beeea6 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -469,8 +469,8 @@ int gpt_fill_pte(struct blk_desc *dev_desc, * If our partition overlaps with either the GPT * header, or the partition entry, reject it. */ - if (((start <= hdr_end && hdr_start <= (start + size)) || - (start <= pte_end && pte_start <= (start + size)))) { + if (((start < hdr_end && hdr_start < (start + size)) || + (start < pte_end && pte_start < (start + size)))) { printf("Partition overlap\n"); return -1; } diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt index a57cdab339..2ece4c47de 100644 --- a/doc/uImage.FIT/signature.txt +++ b/doc/uImage.FIT/signature.txt @@ -85,7 +85,7 @@ allow the signer to operate. These should be added to the .its file. Signature nodes sit at the same level as hash nodes and are called signature@1, signature@2, etc. -- algo: Algorithm name (e.g. "sha1,rs2048") +- algo: Algorithm name (e.g. "sha1,rsa2048") - key-name-hint: Name of key to use for signing. The keys will normally be in a single directory (parameter -k to mkimage). For a given key <name>, its @@ -139,7 +139,7 @@ public key in U-Boot's control FDT (using CONFIG_OF_CONTROL). Public keys should be stored as sub-nodes in a /signature node. Required properties are: -- algo: Algorithm name (e.g. "sha1,rs2048") +- algo: Algorithm name (e.g. "sha1,rsa2048") Optional properties are: diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c index 14803e32b1..5acfa5f0e4 100644 --- a/drivers/core/simple-bus.c +++ b/drivers/core/simple-bus.c @@ -7,8 +7,6 @@ #include <common.h> #include <dm.h> -DECLARE_GLOBAL_DATA_PTR; - struct simple_bus_plat { u32 base; u32 size; diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index e7ade94d91..3a8c61b485 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -10,7 +10,6 @@ obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o -obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o obj-$(CONFIG_I2C_MV) += mv_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o @@ -21,7 +20,6 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o -obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c deleted file mode 100644 index d340639e1a..0000000000 --- a/drivers/i2c/adi_i2c.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * i2c.c - driver for ADI TWI/I2C - * - * Copyright (c) 2006-2014 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.txt for instructions. - */ - -#include <common.h> -#include <console.h> -#include <i2c.h> - -#include <asm/clock.h> -#include <asm/twi.h> -#include <asm/io.h> - -static struct twi_regs *i2c_get_base(struct i2c_adapter *adap); - -/* Every register is 32bit aligned, but only 16bits in size */ -#define ureg(name) u16 name; u16 __pad_##name; -struct twi_regs { - ureg(clkdiv); - ureg(control); - ureg(slave_ctl); - ureg(slave_stat); - ureg(slave_addr); - ureg(master_ctl); - ureg(master_stat); - ureg(master_addr); - ureg(int_stat); - ureg(int_mask); - ureg(fifo_ctl); - ureg(fifo_stat); - char __pad[0x50]; - ureg(xmt_data8); - ureg(xmt_data16); - ureg(rcv_data8); - ureg(rcv_data16); -}; -#undef ureg - -#ifdef TWI_CLKDIV -#define TWI0_CLKDIV TWI_CLKDIV -# ifdef CONFIG_SYS_MAX_I2C_BUS -# undef CONFIG_SYS_MAX_I2C_BUS -# endif -#define CONFIG_SYS_MAX_I2C_BUS 1 -#endif - -/* - * The way speed is changed into duty often results in integer truncation - * with 50% duty, so we'll force rounding up to the next duty by adding 1 - * to the max. In practice this will get us a speed of something like - * 385 KHz. The other limit is easy to handle as it is only 8 bits. - */ -#define I2C_SPEED_MAX 400000 -#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) -#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) -#define I2C_DUTY_MIN 0xff /* 8 bit limited */ -#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) -/* Note: duty is inverse of speed, so the comparisons below are correct */ -#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN -# error "The I2C hardware can only operate 20KHz - 400KHz" -#endif - -/* All transfers are described by this data structure */ -struct adi_i2c_msg { - u8 flags; -#define I2C_M_COMBO 0x4 -#define I2C_M_STOP 0x2 -#define I2C_M_READ 0x1 - int len; /* msg length */ - u8 *buf; /* pointer to msg data */ - int alen; /* addr length */ - u8 *abuf; /* addr buffer */ -}; - -/* Allow msec timeout per ~byte transfer */ -#define I2C_TIMEOUT 10 - -/** - * wait_for_completion - manage the actual i2c transfer - * @msg: the i2c msg - */ -static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg) -{ - u16 int_stat, ctl; - ulong timebase = get_timer(0); - - do { - int_stat = readw(&twi->int_stat); - - if (int_stat & XMTSERV) { - writew(XMTSERV, &twi->int_stat); - if (msg->alen) { - writew(*(msg->abuf++), &twi->xmt_data8); - --msg->alen; - } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { - writew(*(msg->buf++), &twi->xmt_data8); - --msg->len; - } else { - ctl = readw(&twi->master_ctl); - if (msg->flags & I2C_M_COMBO) - writew(ctl | RSTART | MDIR, - &twi->master_ctl); - else - writew(ctl | STOP, &twi->master_ctl); - } - } - if (int_stat & RCVSERV) { - writew(RCVSERV, &twi->int_stat); - if (msg->len) { - *(msg->buf++) = readw(&twi->rcv_data8); - --msg->len; - } else if (msg->flags & I2C_M_STOP) { - ctl = readw(&twi->master_ctl); - writew(ctl | STOP, &twi->master_ctl); - } - } - if (int_stat & MERR) { - writew(MERR, &twi->int_stat); - return msg->len; - } - if (int_stat & MCOMP) { - writew(MCOMP, &twi->int_stat); - if (msg->flags & I2C_M_COMBO && msg->len) { - ctl = readw(&twi->master_ctl); - ctl = (ctl & ~RSTART) | - (min(msg->len, 0xff) << 6) | MEN | MDIR; - writew(ctl, &twi->master_ctl); - } else - break; - } - - /* If we were able to do something, reset timeout */ - if (int_stat) - timebase = get_timer(0); - - } while (get_timer(timebase) < I2C_TIMEOUT); - - return msg->len; -} - -static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr, - int alen, uint8_t *buffer, int len, uint8_t flags) -{ - struct twi_regs *twi = i2c_get_base(adap); - int ret; - u16 ctl; - uchar addr_buffer[] = { - (addr >> 0), - (addr >> 8), - (addr >> 16), - }; - struct adi_i2c_msg msg = { - .flags = flags | (len >= 0xff ? I2C_M_STOP : 0), - .buf = buffer, - .len = len, - .abuf = addr_buffer, - .alen = alen, - }; - - /* wait for things to settle */ - while (readw(&twi->master_stat) & BUSBUSY) - if (ctrlc()) - return 1; - - /* Set Transmit device address */ - writew(chip, &twi->master_addr); - - /* Clear the FIFO before starting things */ - writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl); - writew(0, &twi->fifo_ctl); - - /* prime the pump */ - if (msg.alen) { - len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; - writew(*(msg.abuf++), &twi->xmt_data8); - --msg.alen; - } else if (!(msg.flags & I2C_M_READ) && msg.len) { - writew(*(msg.buf++), &twi->xmt_data8); - --msg.len; - } - - /* clear int stat */ - writew(-1, &twi->master_stat); - writew(-1, &twi->int_stat); - writew(0, &twi->int_mask); - - /* Master enable */ - ctl = readw(&twi->master_ctl); - ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN | - ((msg.flags & I2C_M_READ) ? MDIR : 0); - writew(ctl, &twi->master_ctl); - - /* process the rest */ - ret = wait_for_completion(twi, &msg); - - if (ret) { - ctl = readw(&twi->master_ctl) & ~MEN; - writew(ctl, &twi->master_ctl); - ctl = readw(&twi->control) & ~TWI_ENA; - writew(ctl, &twi->control); - ctl = readw(&twi->control) | TWI_ENA; - writew(ctl, &twi->control); - } - - return ret; -} - -static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed) -{ - struct twi_regs *twi = i2c_get_base(adap); - u16 clkdiv = I2C_SPEED_TO_DUTY(speed); - - /* Set TWI interface clock */ - if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) - return -1; - clkdiv = (clkdiv << 8) | (clkdiv & 0xff); - writew(clkdiv, &twi->clkdiv); - - /* Don't turn it on */ - writew(speed > 100000 ? FAST : 0, &twi->master_ctl); - - return 0; -} - -static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) -{ - struct twi_regs *twi = i2c_get_base(adap); - u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; - - /* Set TWI internal clock as 10MHz */ - writew(prescale, &twi->control); - - /* Set TWI interface clock as specified */ - i2c_set_bus_speed(speed); - - /* Enable it */ - writew(TWI_ENA | prescale, &twi->control); -} - -static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip, - uint addr, int alen, uint8_t *buffer, int len) -{ - return i2c_transfer(adap, chip, addr, alen, buffer, - len, alen ? I2C_M_COMBO : I2C_M_READ); -} - -static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip, - uint addr, int alen, uint8_t *buffer, int len) -{ - return i2c_transfer(adap, chip, addr, alen, buffer, len, 0); -} - -static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip) -{ - u8 byte; - return adi_i2c_read(adap, chip, 0, 0, &byte, 1); -} - -static struct twi_regs *i2c_get_base(struct i2c_adapter *adap) -{ - switch (adap->hwadapnr) { -#if CONFIG_SYS_MAX_I2C_BUS > 2 - case 2: - return (struct twi_regs *)TWI2_CLKDIV; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 1 - case 1: - return (struct twi_regs *)TWI1_CLKDIV; -#endif - case 0: - return (struct twi_regs *)TWI0_CLKDIV; - - default: - printf("wrong hwadapnr: %d\n", adap->hwadapnr); - } - - return NULL; -} - -U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe, - adi_i2c_read, adi_i2c_write, - adi_i2c_setspeed, - CONFIG_SYS_I2C_SPEED, - 0, - 0) - -#if CONFIG_SYS_MAX_I2C_BUS > 1 -U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe, - adi_i2c_read, adi_i2c_write, - adi_i2c_setspeed, - CONFIG_SYS_I2C_SPEED, - 0, - 1) -#endif - -#if CONFIG_SYS_MAX_I2C_BUS > 2 -U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe, - adi_i2c_read, adi_i2c_write, - adi_i2c_setspeed, - CONFIG_SYS_I2C_SPEED, - 0, - 2) -#endif diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c deleted file mode 100644 index 4da959fa53..0000000000 --- a/drivers/i2c/fti2c010.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Faraday I2C Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.txt for instructions. - */ - -#include <common.h> -#include <asm/io.h> -#include <i2c.h> - -#include "fti2c010.h" - -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 5000 -#endif - -#ifndef CONFIG_SYS_I2C_SLAVE -#define CONFIG_SYS_I2C_SLAVE 0 -#endif - -#ifndef CONFIG_FTI2C010_CLOCK -#define CONFIG_FTI2C010_CLOCK clk_get_rate("I2C") -#endif - -#ifndef CONFIG_FTI2C010_TIMEOUT -#define CONFIG_FTI2C010_TIMEOUT 10 /* ms */ -#endif - -/* 7-bit dev address + 1-bit read/write */ -#define I2C_RD(dev) ((((dev) << 1) & 0xfe) | 1) -#define I2C_WR(dev) (((dev) << 1) & 0xfe) - -struct fti2c010_chip { - struct fti2c010_regs *regs; -}; - -static struct fti2c010_chip chip_list[] = { - { - .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE, - }, -#ifdef CONFIG_FTI2C010_BASE1 - { - .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1, - }, -#endif -#ifdef CONFIG_FTI2C010_BASE2 - { - .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2, - }, -#endif -#ifdef CONFIG_FTI2C010_BASE3 - { - .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3, - }, -#endif -}; - -static int fti2c010_reset(struct fti2c010_chip *chip) -{ - ulong ts; - int ret = -1; - struct fti2c010_regs *regs = chip->regs; - - writel(CR_I2CRST, ®s->cr); - for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) { - if (!(readl(®s->cr) & CR_I2CRST)) { - ret = 0; - break; - } - } - - if (ret) - printf("fti2c010: reset timeout\n"); - - return ret; -} - -static int fti2c010_wait(struct fti2c010_chip *chip, uint32_t mask) -{ - int ret = -1; - uint32_t stat, ts; - struct fti2c010_regs *regs = chip->regs; - - for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) { - stat = readl(®s->sr); - if ((stat & mask) == mask) { - ret = 0; - break; - } - } - - return ret; -} - -static unsigned int set_i2c_bus_speed(struct fti2c010_chip *chip, - unsigned int speed) -{ - struct fti2c010_regs *regs = chip->regs; - unsigned int clk = CONFIG_FTI2C010_CLOCK; - unsigned int gsr = 0; - unsigned int tsr = 32; - unsigned int div, rate; - - for (div = 0; div < 0x3ffff; ++div) { - /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */ - rate = clk / (2 * (div + 2) + gsr); - if (rate <= speed) - break; - } - - writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr); - writel(CDR_DIV(div), ®s->cdr); - - return rate; -} - -/* - * Initialization, must be called once on start up, may be called - * repeatedly to change the speed and slave addresses. - */ -static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr) -{ - struct fti2c010_chip *chip = chip_list + adap->hwadapnr; - - if (adap->init_done) - return; - -#ifdef CONFIG_SYS_I2C_INIT_BOARD - /* Call board specific i2c bus reset routine before accessing the - * environment, which might be in a chip on that bus. For details - * about this problem see doc/I2C_Edge_Conditions. - */ - i2c_init_board(); -#endif - - /* master init */ - - fti2c010_reset(chip); - - set_i2c_bus_speed(chip, speed); - - /* slave init, don't care */ -} - -/* - * Probe the given I2C chip address. Returns 0 if a chip responded, - * not 0 on failure. - */ -static int fti2c010_probe(struct i2c_adapter *adap, u8 dev) -{ - struct fti2c010_chip *chip = chip_list + adap->hwadapnr; - struct fti2c010_regs *regs = chip->regs; - int ret; - - /* 1. Select slave device (7bits Address + 1bit R/W) */ - writel(I2C_WR(dev), ®s->dr); - writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); - ret = fti2c010_wait(chip, SR_DT); - if (ret) - return ret; - - /* 2. Select device register */ - writel(0, ®s->dr); - writel(CR_ENABLE | CR_TBEN, ®s->cr); - ret = fti2c010_wait(chip, SR_DT); - - return ret; -} - -static void to_i2c_addr(u8 *buf, uint32_t addr, int alen) -{ - int i, shift; - - if (!buf || alen <= 0) - return; - - /* MSB first */ - i = 0; - shift = (alen - 1) * 8; - while (alen-- > 0) { - buf[i] = (u8)(addr >> shift); - shift -= 8; - } -} - -static int fti2c010_read(struct i2c_adapter *adap, - u8 dev, uint addr, int alen, uchar *buf, int len) -{ - struct fti2c010_chip *chip = chip_list + adap->hwadapnr; - struct fti2c010_regs *regs = chip->regs; - int ret, pos; - uchar paddr[4] = { 0 }; - - to_i2c_addr(paddr, addr, alen); - - /* - * Phase A. Set register address - */ - - /* A.1 Select slave device (7bits Address + 1bit R/W) */ - writel(I2C_WR(dev), ®s->dr); - writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); - ret = fti2c010_wait(chip, SR_DT); - if (ret) - return ret; - - /* A.2 Select device register */ - for (pos = 0; pos < alen; ++pos) { - uint32_t ctrl = CR_ENABLE | CR_TBEN; - - writel(paddr[pos], ®s->dr); - writel(ctrl, ®s->cr); - ret = fti2c010_wait(chip, SR_DT); - if (ret) - return ret; - } - - /* - * Phase B. Get register data - */ - - /* B.1 Select slave device (7bits Address + 1bit R/W) */ - writel(I2C_RD(dev), ®s->dr); - writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); - ret = fti2c010_wait(chip, SR_DT); - if (ret) - return ret; - - /* B.2 Get register data */ - for (pos = 0; pos < len; ++pos) { - uint32_t ctrl = CR_ENABLE | CR_TBEN; - uint32_t stat = SR_DR; - - if (pos == len - 1) { - ctrl |= CR_NAK | CR_STOP; - stat |= SR_ACK; - } - writel(ctrl, ®s->cr); - ret = fti2c010_wait(chip, stat); - if (ret) - break; - buf[pos] = (uchar)(readl(®s->dr) & 0xFF); - } - - return ret; -} - -static int fti2c010_write(struct i2c_adapter *adap, - u8 dev, uint addr, int alen, u8 *buf, int len) -{ - struct fti2c010_chip *chip = chip_list + adap->hwadapnr; - struct fti2c010_regs *regs = chip->regs; - int ret, pos; - uchar paddr[4] = { 0 }; - - to_i2c_addr(paddr, addr, alen); - - /* - * Phase A. Set register address - * - * A.1 Select slave device (7bits Address + 1bit R/W) - */ - writel(I2C_WR(dev), ®s->dr); - writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); - ret = fti2c010_wait(chip, SR_DT); - if (ret) - return ret; - - /* A.2 Select device register */ - for (pos = 0; pos < alen; ++pos) { - uint32_t ctrl = CR_ENABLE | CR_TBEN; - - writel(paddr[pos], ®s->dr); - writel(ctrl, ®s->cr); - ret = fti2c010_wait(chip, SR_DT); - if (ret) - return ret; - } - - /* - * Phase B. Set register data - */ - for (pos = 0; pos < len; ++pos) { - uint32_t ctrl = CR_ENABLE | CR_TBEN; - - if (pos == len - 1) - ctrl |= CR_STOP; - writel(buf[pos], ®s->dr); - writel(ctrl, ®s->cr); - ret = fti2c010_wait(chip, SR_DT); - if (ret) - break; - } - - return ret; -} - -static unsigned int fti2c010_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) -{ - struct fti2c010_chip *chip = chip_list + adap->hwadapnr; - int ret; - - fti2c010_reset(chip); - ret = set_i2c_bus_speed(chip, speed); - - return ret; -} - -/* - * Register i2c adapters - */ -U_BOOT_I2C_ADAP_COMPLETE(i2c_0, fti2c010_init, fti2c010_probe, fti2c010_read, - fti2c010_write, fti2c010_set_bus_speed, - CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - 0) -#ifdef CONFIG_FTI2C010_BASE1 -U_BOOT_I2C_ADAP_COMPLETE(i2c_1, fti2c010_init, fti2c010_probe, fti2c010_read, - fti2c010_write, fti2c010_set_bus_speed, - CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - 1) -#endif -#ifdef CONFIG_FTI2C010_BASE2 -U_BOOT_I2C_ADAP_COMPLETE(i2c_2, fti2c010_init, fti2c010_probe, fti2c010_read, - fti2c010_write, fti2c010_set_bus_speed, - CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - 2) -#endif -#ifdef CONFIG_FTI2C010_BASE3 -U_BOOT_I2C_ADAP_COMPLETE(i2c_3, fti2c010_init, fti2c010_probe, fti2c010_read, - fti2c010_write, fti2c010_set_bus_speed, - CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - 3) -#endif diff --git a/drivers/i2c/fti2c010.h b/drivers/i2c/fti2c010.h deleted file mode 100644 index b9d0eb74a6..0000000000 --- a/drivers/i2c/fti2c010.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Faraday I2C Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FTI2C010_H -#define __FTI2C010_H - -/* - * FTI2C010 registers - */ -struct fti2c010_regs { - uint32_t cr; /* 0x00: control register */ - uint32_t sr; /* 0x04: status register */ - uint32_t cdr; /* 0x08: clock division register */ - uint32_t dr; /* 0x0c: data register */ - uint32_t sar; /* 0x10: slave address register */ - uint32_t tgsr;/* 0x14: time & glitch suppression register */ - uint32_t bmr; /* 0x18: bus monitor register */ - uint32_t rsvd[5]; - uint32_t revr;/* 0x30: revision register */ -}; - -/* - * control register - */ -#define CR_ALIRQ 0x2000 /* arbitration lost interrupt (master) */ -#define CR_SAMIRQ 0x1000 /* slave address match interrupt (slave) */ -#define CR_STOPIRQ 0x800 /* stop condition interrupt (slave) */ -#define CR_NAKRIRQ 0x400 /* NACK response interrupt (master) */ -#define CR_DRIRQ 0x200 /* rx interrupt (both) */ -#define CR_DTIRQ 0x100 /* tx interrupt (both) */ -#define CR_TBEN 0x80 /* tx enable (both) */ -#define CR_NAK 0x40 /* NACK (both) */ -#define CR_STOP 0x20 /* stop (master) */ -#define CR_START 0x10 /* start (master) */ -#define CR_GCEN 0x8 /* general call support (slave) */ -#define CR_SCLEN 0x4 /* enable clock out (master) */ -#define CR_I2CEN 0x2 /* enable I2C (both) */ -#define CR_I2CRST 0x1 /* reset I2C (both) */ -#define CR_ENABLE \ - (CR_ALIRQ | CR_NAKRIRQ | CR_DRIRQ | CR_DTIRQ | CR_SCLEN | CR_I2CEN) - -/* - * status register - */ -#define SR_CLRAL 0x400 /* clear arbitration lost */ -#define SR_CLRGC 0x200 /* clear general call */ -#define SR_CLRSAM 0x100 /* clear slave address match */ -#define SR_CLRSTOP 0x80 /* clear stop */ -#define SR_CLRNAKR 0x40 /* clear NACK respond */ -#define SR_DR 0x20 /* rx ready */ -#define SR_DT 0x10 /* tx done */ -#define SR_BB 0x8 /* bus busy */ -#define SR_BUSY 0x4 /* chip busy */ -#define SR_ACK 0x2 /* ACK/NACK received */ -#define SR_RW 0x1 /* set when master-rx or slave-tx mode */ - -/* - * clock division register - */ -#define CDR_DIV(n) ((n) & 0x3ffff) - -/* - * time & glitch suppression register - */ -#define TGSR_GSR(n) (((n) & 0x7) << 10) -#define TGSR_TSR(n) ((n) & 0x3ff) - -/* - * bus monitor register - */ -#define BMR_SCL 0x2 /* SCL is pull-up */ -#define BMR_SDA 0x1 /* SDA is pull-up */ - -#endif /* __FTI2C010_H */ diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 7c10bfedc6..65dd83eced 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -702,7 +702,7 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host, if (chip->onfi_version) { *cap = chip->ecc_strength_ds; *sector_size = chip->ecc_step_ds; - MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n", + pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n", *cap, *sector_size); } @@ -863,9 +863,8 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024; #endif - MTDDEBUG(MTD_DEBUG_LEVEL1, - "Initialize PMECC params, cap: %d, sector: %d\n", - cap, sector_size); + pr_debug("Initialize PMECC params, cap: %d, sector: %d\n", + cap, sector_size); host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC; host->pmerrloc = (struct pmecc_errloc_regs __iomem *) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 0624644581..2a01fd34e9 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -238,7 +238,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, uint32_t find_byte = diff >> (12 + 3); dat[find_byte] ^= find_bit; - MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single " + pr_debug("Correcting single " "bit ECC error at offset: %d, bit: " "%d\n", find_byte, find_bit); return 1; @@ -248,12 +248,11 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, } else if (!(diff & (diff - 1))) { /* Single bit ECC error in the ECC itself, nothing to fix */ - MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in " - "ECC.\n"); + pr_debug("Single bit ECC error in " "ECC.\n"); return 1; } else { /* Uncorrectable error */ - MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); + pr_debug("ECC UNCORRECTED_ERROR 1\n"); return -EBADMSG; } } diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 7221d0ba0d..764391c8d2 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -132,7 +132,7 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries, udelay(1); } if (max_retries < 0) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n", + pr_debug("%s(%d): INT not set\n", __func__, param); } } @@ -143,7 +143,7 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries, */ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd) { - MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd); + pr_debug("send_cmd(host, 0x%x)\n", cmd); writenfc(cmd, &host->regs->flash_cmd); writenfc(NFC_CMD, &host->regs->operation); @@ -159,7 +159,7 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd) */ static void send_addr(struct mxc_nand_host *host, uint16_t addr) { - MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr); + pr_debug("send_addr(host, 0x%x)\n", addr); writenfc(addr, &host->regs->flash_addr); writenfc(NFC_ADDR, &host->regs->operation); @@ -176,7 +176,7 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, int spare_only) { if (spare_only) - MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only); + pr_debug("send_prog_page (%d)\n", spare_only); if (is_mxc_nfc_21() || is_mxc_nfc_32()) { int i; @@ -226,7 +226,7 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, int spare_only) { - MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only); + pr_debug("send_read_page (%d)\n", spare_only); #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) writenfc(buf_id, &host->regs->buf_addr); @@ -392,8 +392,7 @@ static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd, uint8_t *bufpoi = buf; int i, toread; - MTDDEBUG(MTD_DEBUG_LEVEL0, - "%s: Reading OOB area of page %u to oob %p\n", + pr_debug("%s: Reading OOB area of page %u to oob %p\n", __func__, page, buf); chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page); @@ -493,8 +492,8 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd, uint8_t *p = buf; uint8_t *oob = chip->oob_poi; - MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n", - page, buf, oob); + pr_debug("Reading page %u to buf %p oob %p\n", + page, buf, oob); /* first read the data area and the available portion of OOB */ for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) { @@ -710,8 +709,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, uint16_t ecc_status = readnfc(&host->regs->ecc_status_result); if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { - MTDDEBUG(MTD_DEBUG_LEVEL0, - "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); + pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); return -EBADMSG; } @@ -773,8 +771,7 @@ static uint16_t mxc_nand_read_word(struct mtd_info *mtd) uint16_t col, ret; uint16_t __iomem *p; - MTDDEBUG(MTD_DEBUG_LEVEL3, - "mxc_nand_read_word(col = %d)\n", host->col_addr); + pr_debug("mxc_nand_read_word(col = %d)\n", host->col_addr); col = host->col_addr; /* Adjust saved column address */ @@ -824,9 +821,8 @@ static void mxc_nand_write_buf(struct mtd_info *mtd, struct mxc_nand_host *host = nand_get_controller_data(nand_chip); int n, col, i = 0; - MTDDEBUG(MTD_DEBUG_LEVEL3, - "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr, - len); + pr_debug("mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr, + len); col = host->col_addr; @@ -837,8 +833,7 @@ static void mxc_nand_write_buf(struct mtd_info *mtd, n = mtd->writesize + mtd->oobsize - col; n = min(len, n); - MTDDEBUG(MTD_DEBUG_LEVEL3, - "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n); + pr_debug("%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n); while (n > 0) { void __iomem *p; @@ -850,8 +845,8 @@ static void mxc_nand_write_buf(struct mtd_info *mtd, mtd->writesize + (col & ~3); } - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__, - __LINE__, p); + pr_debug("%s:%d: p = %p\n", __func__, + __LINE__, p); if (((col | (unsigned long)&buf[i]) & 3) || n < 4) { union { @@ -873,9 +868,8 @@ static void mxc_nand_write_buf(struct mtd_info *mtd, m = min(n, m) & ~3; - MTDDEBUG(MTD_DEBUG_LEVEL3, - "%s:%d: n = %d, m = %d, i = %d, col = %d\n", - __func__, __LINE__, n, m, i, col); + pr_debug("%s:%d: n = %d, m = %d, i = %d, col = %d\n", + __func__, __LINE__, n, m, i, col); mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m); col += m; @@ -898,8 +892,8 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) struct mxc_nand_host *host = nand_get_controller_data(nand_chip); int n, col, i = 0; - MTDDEBUG(MTD_DEBUG_LEVEL3, - "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len); + pr_debug("mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, + len); col = host->col_addr; @@ -984,9 +978,8 @@ void mxc_nand_command(struct mtd_info *mtd, unsigned command, struct nand_chip *nand_chip = mtd_to_nand(mtd); struct mxc_nand_host *host = nand_get_controller_data(nand_chip); - MTDDEBUG(MTD_DEBUG_LEVEL3, - "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", - command, column, page_addr); + pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", + command, column, page_addr); /* Reset command state information */ host->status_request = false; diff --git a/drivers/mtd/nand/nand_bch.c b/drivers/mtd/nand/nand_bch.c index c14520380e..6c20d53e7e 100644 --- a/drivers/mtd/nand/nand_bch.c +++ b/drivers/mtd/nand/nand_bch.c @@ -81,8 +81,8 @@ int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf, buf[errloc[i] >> 3] ^= (1 << (errloc[i] & 7)); /* else error in ecc, no action needed */ - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: corrected bitflip %u\n", - __func__, errloc[i]); + pr_debug("%s: corrected bitflip %u\n", + __func__, errloc[i]); } } else if (count < 0) { printk(KERN_ERR "ecc unrecoverable error\n"); diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 8282f683a5..86b1640357 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -858,7 +858,8 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, int ret = 0, boundary = 0; int writesize = this->writesize; - MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ops_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + pr_debug("onenand_read_ops_nolock: from = 0x%08x, len = %i\n", + (unsigned int) from, (int) len); if (ops->mode == MTD_OPS_AUTO_OOB) oobsize = this->ecclayout->oobavail; @@ -1007,7 +1008,8 @@ static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from, from += ops->ooboffs; - MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + pr_debug("onenand_read_oob_nolock: from = 0x%08x, len = %i\n", + (unsigned int) from, (int) len); /* Initialize return length value */ ops->oobretlen = 0; @@ -1214,7 +1216,8 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, size_t len = ops->ooblen; u_char *buf = ops->oobbuf; - MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", (unsigned int) from, len); + pr_debug("onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", + (unsigned int) from, len); readcmd = ONENAND_IS_4KB_PAGE(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB; @@ -1417,7 +1420,8 @@ static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to, u_char *oobbuf; int ret = 0; - MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ops_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + pr_debug("onenand_write_ops_nolock: to = 0x%08x, len = %i\n", + (unsigned int) to, (int) len); /* Initialize retlen, in case of early exit */ ops->retlen = 0; @@ -1538,7 +1542,8 @@ static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, to += ops->ooboffs; - MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + pr_debug("onenand_write_oob_nolock: to = 0x%08x, len = %i\n", + (unsigned int) to, (int) len); /* Initialize retlen, in case of early exit */ ops->oobretlen = 0; @@ -1730,7 +1735,7 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) struct mtd_erase_region_info *region = NULL; unsigned int region_end = 0; - MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", + pr_debug("onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) addr, len); if (FLEXONENAND(this)) { @@ -1746,8 +1751,7 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) * Erase region's start offset is always block start address. */ if (unlikely((addr - region->offset) & (block_size - 1))) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:" - " Unaligned address\n"); + pr_debug("onenand_erase:" " Unaligned address\n"); return -EINVAL; } } else { @@ -1755,16 +1759,14 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) /* Start address must align on block boundary */ if (unlikely(addr & (block_size - 1))) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:" - "Unaligned address\n"); + pr_debug("onenand_erase:" "Unaligned address\n"); return -EINVAL; } } /* Length must align on block boundary */ if (unlikely(len & (block_size - 1))) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_erase: Length not block aligned\n"); + pr_debug("onenand_erase: Length not block aligned\n"); return -EINVAL; } @@ -1793,12 +1795,12 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) /* Check, if it is write protected */ if (ret) { if (ret == -EPERM) - MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_erase: " - "Device is write protected!!!\n"); + pr_debug("onenand_erase: " + "Device is write protected!!!\n"); else - MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_erase: " - "Failed erase, block %d\n", - onenand_block(this, addr)); + pr_debug("onenand_erase: " + "Failed erase, block %d\n", + onenand_block(this, addr)); instr->state = MTD_ERASE_FAILED; instr->fail_addr = addr; @@ -1849,7 +1851,7 @@ erase_exit: */ void onenand_sync(struct mtd_info *mtd) { - MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); + pr_debug("onenand_sync: called\n"); /* Grab the lock and see if the device is available */ onenand_get_device(mtd, FL_SYNCING); diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c index 20507004ed..cde342aaec 100644 --- a/drivers/mtd/onenand/onenand_bbt.c +++ b/drivers/mtd/onenand/onenand_bbt.c @@ -160,9 +160,8 @@ static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) block = (int) (onenand_block(this, offs) << 1); res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03; - MTDDEBUG (MTD_DEBUG_LEVEL2, - "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n", - (unsigned int)offs, block >> 1, res); + pr_debug("onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n", + (unsigned int)offs, block >> 1, res); switch ((int)res) { case 0x00: diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 5700859ff2..6ba255d676 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -140,6 +140,7 @@ if SPL config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I + select SPL_SPI_FLASH_SUPPORT ---help--- Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 4df9eda086..21705c8478 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -100,7 +100,7 @@ static int mc146818_get(struct rtc_time *tmp) #ifdef RTC_DEBUG printf("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x hr: %02x min: %02x sec: %02x\n", year, mon, mday, wday, hour, min, sec); - printf("Alarms: month: %02x hour: %02x min: %02x sec: %02x\n", + printf("Alarms: mday: %02x hour: %02x min: %02x sec: %02x\n", mc146818_read8(RTC_CONFIG_D) & 0x3f, mc146818_read8(RTC_HOURS_ALARM), mc146818_read8(RTC_MINUTES_ALARM), diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 22fc83dd72..927bbd708f 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -184,6 +184,19 @@ static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) trans->bytesin -= bytes; } +static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase) +{ + if (plat->ich_version == ICHV_7) { + struct ich7_spi_regs *ich7_spi = sbase; + + setbits_le16(&ich7_spi->spis, SPIS_LOCK); + } else if (plat->ich_version == ICHV_9) { + struct ich9_spi_regs *ich9_spi = sbase; + + setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN); + } +} + static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase) { int lock = 0; @@ -592,6 +605,12 @@ static int ich_spi_probe(struct udevice *dev) return ret; } + /* Lock down SPI controller settings if required */ + if (plat->lockdown) { + ich_spi_config_opcode(dev); + spi_lock_down(plat, priv->base); + } + priv->cur_speed = priv->max_speed; return 0; @@ -662,6 +681,9 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) plat->ich_version = ICHV_9; } + plat->lockdown = fdtdec_get_bool(gd->fdt_blob, node, + "intel,spi-lock-down"); + return ret; } diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index c867c57be9..06b7fb9e01 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -174,6 +174,7 @@ enum ich_version { struct ich_spi_platdata { enum ich_version ich_version; /* Controller version, 7 or 9 */ + bool lockdown; /* lock down controller settings? */ }; struct ich_spi_priv { diff --git a/env/Kconfig b/env/Kconfig index 02cb7cbb75..8c9d800f48 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -16,6 +16,7 @@ choice default ENV_IS_IN_FLASH if SH && !CPU_SH4 default ENV_IS_IN_SPI_FLASH if ARMADA_XP default ENV_IS_IN_SPI_FLASH if INTEL_BAYTRAIL + default ENV_IS_IN_SPI_FLASH if INTEL_BRASWELL default ENV_IS_IN_SPI_FLASH if INTEL_BROADWELL default ENV_IS_IN_SPI_FLASH if NORTHBRIDGE_INTEL_IVYBRIDGE default ENV_IS_IN_SPI_FLASH if INTEL_QUARK diff --git a/fs/ubifs/debug.h b/fs/ubifs/debug.h index 807ce1b733..98140834f9 100644 --- a/fs/ubifs/debug.h +++ b/fs/ubifs/debug.h @@ -187,19 +187,12 @@ struct ubifs_global_debug_info { ##__VA_ARGS__) #define DBG_KEY_BUF_LEN 48 -#if defined CONFIG_MTD_DEBUG #define ubifs_dbg_msg_key(type, key, fmt, ...) do { \ char __tmp_key_buf[DBG_KEY_BUF_LEN]; \ pr_debug("UBIFS DBG " type ": " fmt "%s\n", \ ##__VA_ARGS__, \ dbg_snprintf_key(c, key, __tmp_key_buf, DBG_KEY_BUF_LEN)); \ } while (0) -#else -#define ubifs_dbg_msg_key(type, key, fmt, ...) do { \ - pr_debug("UBIFS DBG\n"); \ -} while (0) - -#endif #endif diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index d6982d31a9..7e805ecff0 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -109,7 +109,6 @@ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_ENABLE_36BIT_PHYS diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 13edd0ac9c..adb4a18a70 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -205,7 +205,6 @@ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_ENABLE_36BIT_PHYS diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 2eeb3d1420..32439f5c47 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -266,7 +266,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI #define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h index ab3d40c892..717ec80f82 100644 --- a/include/configs/ap_sh4a_4a.h +++ b/include/configs/ap_sh4a_4a.h @@ -12,7 +12,6 @@ #define CONFIG_CPU_SH7734 1 #define CONFIG_AP_SH4A_4A 1 #define CONFIG_400MHZ_MODE 1 -/* #define CONFIG_533MHZ_MODE 1 */ #define CONFIG_SYS_TEXT_BASE 0x8BFC0000 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 111a7dce7d..67115f981b 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -72,7 +72,6 @@ #define CONFIG_ATMEL_NAND_HW_PMECC #define CONFIG_PMECC_CAP 2 #define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000 #define CONFIG_MTD_PARTITIONS #define CONFIG_MTD_DEVICE diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h index 3b65416dcf..03700b0b7b 100644 --- a/include/configs/bg0900.h +++ b/include/configs/bg0900.h @@ -27,7 +27,6 @@ /* SPI */ #ifdef CONFIG_CMD_SPI #define CONFIG_DEFAULT_SPI_BUS 2 -#define CONFIG_DEFAULT_SPI_CS 0 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 /* SPI FLASH */ diff --git a/include/configs/blanche.h b/include/configs/blanche.h index 2b18033e64..ce7c716465 100755 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -65,7 +65,6 @@ #undef CONFIG_CMD_SPI #endif -#define CONFIG_NET_MULTI /* Board Clock */ #define RMOBILE_XTAL_CLK 20000000u diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index 80d4e49f6d..ff66518231 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -45,7 +45,7 @@ "boot_fdt=try\0" \ "console=ttyO0,115200n8\0" \ "image=zImage\0" \ - "fdt_file=am335x-chiliboard.dtb\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "ip_dyn=yes\0" \ "optargs=\0" \ "loadbootscript=" \ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 7012a95fd7..a2224915e7 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -50,7 +50,6 @@ #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_GATEWAY -#define CONFIG_NET_MULTI #define CONFIG_PHY_ATHEROS #define CONFIG_SYS_RX_ETH_BUFFER 64 diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 13e7c71609..1b20d85acf 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -370,7 +370,6 @@ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index c9584ad71c..7bd2c4aad4 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -120,7 +120,6 @@ -#define CONFIG_DFU_MTD #undef COMMON_ENV_DFU_ARGS #define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ "setenv bootargs ${bootargs};" \ diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 79e6d13491..ae9ead53f6 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -43,11 +43,6 @@ #define CONFIG_LOWPOWER_FLAG 0x02020028 #define CONFIG_LOWPOWER_ADDR 0x0202002C -/* - * Number of CPUs available - */ -#define CONFIG_CORE_COUNT 0x8 - #define CONFIG_USB_XHCI_EXYNOS #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index 0aeec3900a..4e104718be 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -43,9 +43,6 @@ #define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE) #define CPU_RELEASE_ADDR secondary_boot_addr -/* Number of CPUs available */ -#define CONFIG_CORE_COUNT 0x8 - /* select serial console configuration */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index ffb512db45..d15054709e 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -138,7 +138,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_MEMINFO diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 0caa474636..794117062f 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -53,7 +53,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_MEMINFO diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index a29713499b..a24d0062d2 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -165,7 +165,6 @@ #define CONFIG_PCIE3 /* PCIE controller 3 */ #ifdef CONFIG_PCI -#define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW #endif #endif diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 4fcf4805ee..b5ba6b43d7 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -72,7 +72,6 @@ /* SPI */ #ifdef CONFIG_CMD_SPI #define CONFIG_DEFAULT_SPI_BUS 2 -#define CONFIG_DEFAULT_SPI_CS 0 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 /* SPI FLASH */ diff --git a/include/configs/novena.h b/include/configs/novena.h index ac00975a8c..3acc8c62de 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -80,7 +80,6 @@ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index 896c32996c..9c84acc89c 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -67,7 +67,6 @@ /* Ethernet driver configuration */ #ifdef CONFIG_CMD_NET #define CONFIG_NETCONSOLE -#define CONFIG_NET_MULTI #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 1 #define CONFIG_RESET_PHY_R diff --git a/include/configs/nsim.h b/include/configs/nsim.h index c086de6aa7..c4775e539f 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -30,7 +30,6 @@ * */ #define CONFIG_ARC_SERIAL -#define CONFIG_ARC_UART_BASE 0xC0FC1000 /* * Command line configuration diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index c89bd13f55..c7f7131cbc 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -16,7 +16,6 @@ /* * High Level Configuration Options */ -#define CONFIG_4430SDP 1 /* working with SDP */ #define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP #include <configs/ti_omap4_common.h> diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 570c375cdc..2fa280e7ee 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -182,9 +182,6 @@ /* Disable CPSW SPL support so we fit within the 101KiB limit. */ #endif -/* CPSW ethernet */ -#define CONFIG_NET_MULTI - /* Network */ #define CONFIG_PHY_RESET 1 #define CONFIG_PHY_NATSEMI diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h index a31c6e20df..1fef8b5f92 100644 --- a/include/configs/r0p7734.h +++ b/include/configs/r0p7734.h @@ -12,7 +12,6 @@ #define CONFIG_CPU_SH7734 1 #define CONFIG_R0P7734 1 #define CONFIG_400MHZ_MODE 1 -/* #define CONFIG_533MHZ_MODE 1 */ #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 9859f30718..7ecaefbc8c 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -170,7 +170,6 @@ int universal_spi_read(void); /* Download menu - Samsung common */ #define CONFIG_LCD_MENU -#define CONFIG_LCD_MENU_BOARD /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 5bf5731029..77a12de963 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -25,7 +25,6 @@ /* use to RPC(SPI Multi I/O Bus Controller) */ /* Ethernet RAVB */ -#define CONFIG_NET_MULTI #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 7b5417a75b..7281bda6ac 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -94,7 +94,6 @@ #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII -#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) #endif /* diff --git a/include/configs/trats.h b/include/configs/trats.h index 5b33a3b18e..a34c349bb3 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -180,7 +180,6 @@ /* Download menu - Samsung common */ #define CONFIG_LCD_MENU -#define CONFIG_LCD_MENU_BOARD /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 95c011f9a9..6b371f4ab9 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -162,7 +162,6 @@ /* Download menu - Samsung common */ #define CONFIG_LCD_MENU -#define CONFIG_LCD_MENU_BOARD /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index cce245613d..b54e63c2a2 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -33,7 +33,6 @@ /* use to RPC(SPI Multi I/O Bus Controller) */ /* Ethernet RAVB */ -#define CONFIG_NET_MULTI #define CONFIG_PHY_MICREL #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 8ea5e48483..67c936721d 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -178,10 +178,6 @@ #define CONFIG_MXC_NAND_HWECC #define CONFIG_SYS_NAND_LARGEPAGE -#if 0 -#define CONFIG_MTD_DEBUG -#define CONFIG_MTD_DEBUG_VERBOSE 7 -#endif #define CONFIG_SYS_NAND_ONFI_DETECTION /* diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 1399dfd436..8526ba0e88 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -131,7 +131,6 @@ /* Ethernet driver */ #if defined(CONFIG_ZYNQ_GEM) -# define CONFIG_NET_MULTI # define CONFIG_MII # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_PHY_MARVELL diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index b433224041..6c0981b113 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -204,7 +204,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_FDT_FIXUP_PCI_IRQ 1 /* * I2C diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 3e1694b3a5..4bde251322 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -442,30 +442,6 @@ static inline void mtd_erase_callback(struct erase_info *instr) } #endif -#ifdef __UBOOT__ -/* - * Debugging macro and defines - */ -#define MTD_DEBUG_LEVEL0 (0) /* Quiet */ -#define MTD_DEBUG_LEVEL1 (1) /* Audible */ -#define MTD_DEBUG_LEVEL2 (2) /* Loud */ -#define MTD_DEBUG_LEVEL3 (3) /* Noisy */ - -#ifdef CONFIG_MTD_DEBUG -#define MTDDEBUG(n, args...) \ - do { \ - if (n <= CONFIG_MTD_DEBUG_VERBOSE) \ - printk(KERN_INFO args); \ - } while(0) -#else /* CONFIG_MTD_DEBUG */ -#define MTDDEBUG(n, args...) \ - do { \ - if (0) \ - printk(KERN_INFO args); \ - } while(0) -#endif /* CONFIG_MTD_DEBUG */ -#endif - static inline int mtd_is_bitflip(int err) { return err == -EUCLEAN; } diff --git a/test/py/README.md b/test/py/README.md index ea4b66a41c..eefac37756 100644 --- a/test/py/README.md +++ b/test/py/README.md @@ -11,7 +11,7 @@ results. Advantages of this approach are: U-Boot; there can be no disconnect. - There is no need to write or embed test-related code into U-Boot itself. It is asserted that writing test-related code in Python is simpler and more - flexible that writing it all in C. + flexible than writing it all in C. - It is reasonably simple to interact with U-Boot in this way. ## Requirements @@ -183,7 +183,7 @@ The following environment variables are set when running hook scripts: - `UBOOT_TEST_PY_DIR` the full path to `test/py/` in the source directory. - `UBOOT_BUILD_DIR` the U-Boot build directory. - `UBOOT_RESULT_DIR` the test result directory. -- `UBOOT_PERSISTENT_DATA_DIR` the test peristent data directory. +- `UBOOT_PERSISTENT_DATA_DIR` the test persistent data directory. #### `u-boot-test-console` @@ -222,7 +222,7 @@ the following cases: from there. Use of this feature will reduce wear on the board's flash, so may be preferable if available, and if cold boot testing of U-Boot is not required. If this feature is used, the `u-boot-test-reset` script should - peform this download, since the board could conceivably be reset multiple + perform this download, since the board could conceivably be reset multiple times in a single test run. It is up to the user to determine if those situations exist, and to code this diff --git a/test/py/tests/test_gpt.py b/test/py/tests/test_gpt.py index ec25fbbc5a..b9b5e5fbb0 100644 --- a/test/py/tests/test_gpt.py +++ b/test/py/tests/test_gpt.py @@ -28,26 +28,31 @@ class GptTestDiskImage(object): """ filename = 'test_gpt_disk_image.bin' - self.path = u_boot_console.config.persistent_data_dir + '/' + filename - if os.path.exists(self.path): - u_boot_console.log.action('Disk image file ' + self.path + + persistent = u_boot_console.config.persistent_data_dir + '/' + filename + self.path = u_boot_console.config.result_dir + '/' + filename + + if os.path.exists(persistent): + u_boot_console.log.action('Disk image file ' + persistent + ' already exists') else: - u_boot_console.log.action('Generating ' + self.path) - fd = os.open(self.path, os.O_RDWR | os.O_CREAT) + u_boot_console.log.action('Generating ' + persistent) + fd = os.open(persistent, os.O_RDWR | os.O_CREAT) os.ftruncate(fd, 4194304) os.close(fd) cmd = ('sgdisk', '-U', '375a56f7-d6c9-4e81-b5f0-09d41ca89efe', - self.path) + persistent) u_boot_utils.run_and_log(u_boot_console, cmd) - cmd = ('sgdisk', '--new=1:2048:2560', self.path) + cmd = ('sgdisk', '--new=1:2048:2560', '-c 1:part1', persistent) u_boot_utils.run_and_log(u_boot_console, cmd) - cmd = ('sgdisk', '--new=2:4096:4608', self.path) + cmd = ('sgdisk', '--new=2:4096:4608', '-c 2:part2', persistent) u_boot_utils.run_and_log(u_boot_console, cmd) - cmd = ('sgdisk', '-l', self.path) + cmd = ('sgdisk', '-l', persistent) u_boot_utils.run_and_log(u_boot_console, cmd) + cmd = ('cp', persistent, self.path) + u_boot_utils.run_and_log(u_boot_console, cmd) + gtdi = None @pytest.fixture(scope='function') def state_disk_image(u_boot_console): @@ -63,6 +68,33 @@ def state_disk_image(u_boot_console): @pytest.mark.boardspec('sandbox') @pytest.mark.buildconfigspec('cmd_gpt') +@pytest.mark.buildconfigspec('cmd_part') +@pytest.mark.requiredtool('sgdisk') +def test_gpt_read(state_disk_image, u_boot_console): + """Test the gpt read command.""" + + u_boot_console.run_command('host bind 0 ' + state_disk_image.path) + output = u_boot_console.run_command('gpt read host 0') + assert 'Start 1MiB, size 0MiB' in output + assert 'Block size 512, name part1' in output + assert 'Start 2MiB, size 0MiB' in output + assert 'Block size 512, name part2' in output + output = u_boot_console.run_command('part list host 0') + assert '0x00000800 0x00000a00 "part1"' in output + assert '0x00001000 0x00001200 "part2"' in output + +@pytest.mark.boardspec('sandbox') +@pytest.mark.buildconfigspec('cmd_gpt') +@pytest.mark.requiredtool('sgdisk') +def test_gpt_verify(state_disk_image, u_boot_console): + """Test the gpt verify command.""" + + u_boot_console.run_command('host bind 0 ' + state_disk_image.path) + output = u_boot_console.run_command('gpt verify host 0') + assert 'Verify GPT: success!' in output + +@pytest.mark.boardspec('sandbox') +@pytest.mark.buildconfigspec('cmd_gpt') @pytest.mark.requiredtool('sgdisk') def test_gpt_guid(state_disk_image, u_boot_console): """Test the gpt guid command.""" @@ -87,6 +119,7 @@ def test_gpt_save_guid(state_disk_image, u_boot_console): @pytest.mark.boardspec('sandbox') @pytest.mark.buildconfigspec('cmd_gpt') @pytest.mark.buildconfigspec('cmd_gpt_rename') +@pytest.mark.buildconfigspec('cmd_part') @pytest.mark.requiredtool('sgdisk') def test_gpt_rename_partition(state_disk_image, u_boot_console): """Test the gpt rename command to write partition names.""" @@ -98,6 +131,9 @@ def test_gpt_rename_partition(state_disk_image, u_boot_console): u_boot_console.run_command('gpt rename host 0 2 second') output = u_boot_console.run_command('gpt read host 0') assert 'name second' in output + output = u_boot_console.run_command('part list host 0') + assert '0x00000800 0x00000a00 "first"' in output + assert '0x00001000 0x00001200 "second"' in output @pytest.mark.boardspec('sandbox') @pytest.mark.buildconfigspec('cmd_gpt') @@ -109,9 +145,29 @@ def test_gpt_swap_partitions(state_disk_image, u_boot_console): u_boot_console.run_command('host bind 0 ' + state_disk_image.path) output = u_boot_console.run_command('part list host 0') - assert '0x000007ff "first"' in output - assert '0x000017ff "second"' in output + assert '0x00000800 0x00000a00 "first"' in output + assert '0x00001000 0x00001200 "second"' in output u_boot_console.run_command('gpt swap host 0 first second') output = u_boot_console.run_command('part list host 0') - assert '0x000007ff "second"' in output - assert '0x000017ff "first"' in output + assert '0x00000800 0x00000a00 "second"' in output + assert '0x00001000 0x00001200 "first"' in output + +@pytest.mark.boardspec('sandbox') +@pytest.mark.buildconfigspec('cmd_gpt') +@pytest.mark.buildconfigspec('cmd_part') +@pytest.mark.requiredtool('sgdisk') +def test_gpt_write(state_disk_image, u_boot_console): + """Test the gpt write command.""" + + u_boot_console.run_command('host bind 0 ' + state_disk_image.path) + output = u_boot_console.run_command('gpt write host 0 "name=all,size=0"') + assert 'Writing GPT: success!' in output + output = u_boot_console.run_command('part list host 0') + assert '0x00000022 0x00001fde "all"' in output + output = u_boot_console.run_command('gpt write host 0 "uuid_disk=375a56f7-d6c9-4e81-b5f0-09d41ca89efe;name=first,start=0x100000,size=0x40200;name=second,start=0x200000,size=0x40200;"') + assert 'Writing GPT: success!' in output + output = u_boot_console.run_command('part list host 0') + assert '0x00000800 0x00000a00 "first"' in output + assert '0x00001000 0x00001200 "second"' in output + output = u_boot_console.run_command('gpt guid host 0') + assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output diff --git a/tools/image-host.c b/tools/image-host.c index 5e4d690714..c60d4adb3d 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -513,7 +513,7 @@ static int fit_config_get_data(void *fit, int conf_noffset, int noffset, int ret, len; conf_name = fit_get_name(fit, conf_noffset, NULL); - sig_name = fit_get_name(fit, conf_noffset, NULL); + sig_name = fit_get_name(fit, noffset, NULL); debug("%s: conf='%s', sig='%s'\n", __func__, conf_name, sig_name); /* Get a list of nodes we want to hash */ |