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authorCooper Jr., Franklin <fcooper@ti.com>2017-06-16 17:25:21 -0500
committerTom Rini <trini@konsulko.com>2017-07-10 14:25:57 -0400
commite5e546aad18a725787e6c6b6aa1383b02eed0723 (patch)
treee6ec3a19bdb5e70439a7256686de0a65541c269b /board/ti
parenta76a6f3e0434b68de30fbdf2825dea8060d066fd (diff)
ARM: k2g: Program DDRPHY_DATX8 registers via mask and value variables
Different K2G evms may need to program the various KS2_DDRPHY_DATX8_X_OFFSET registers in different ways. Therefore, use the mask and val registers for each KS2_DDRPHY_DATAX_X_OFFSET to properly program the register. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board/ti')
-rw-r--r--board/ti/ks2_evm/ddr3_k2g.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
index aeb7da6bd1..3b12943237 100644
--- a/board/ti/ks2_evm/ddr3_k2g.c
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -34,6 +34,20 @@ struct ddr3_phy_config ddr3phy_800_2g = {
.zq1cr1 = 0x0001005Bul,
.zq2cr1 = 0x0001005Bul,
.pir_v1 = 0x00000033ul,
+ .datx8_2_mask = 0,
+ .datx8_2_val = 0,
+ .datx8_3_mask = 0,
+ .datx8_3_val = 0,
+ .datx8_4_mask = 0,
+ .datx8_4_val = ((1 << 0)),
+ .datx8_5_mask = DXEN_MASK,
+ .datx8_5_val = 0,
+ .datx8_6_mask = DXEN_MASK,
+ .datx8_6_val = 0,
+ .datx8_7_mask = DXEN_MASK,
+ .datx8_7_val = 0,
+ .datx8_8_mask = DXEN_MASK,
+ .datx8_8_val = 0,
.pir_v2 = 0x00000F81ul,
};