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authorÁlvaro Fernández Rojas <noltari@gmail.com>2017-05-07 20:09:33 +0200
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2017-05-10 16:16:09 +0200
commitc9c94d5d7e8ca6a9578732cecc15710bad0cb319 (patch)
tree7e0bc74a863738aafded94dd94a1e7c349f92eab /arch
parent320186f4768a6a8445909031fa4646e455940862 (diff)
mips: bmips: add bcm6345-gpio driver support for BCM63268
This SoC has one gpio bank divided into two 32 bit registers, with a total of 52 GPIOs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/dts/brcm,bcm63268.dtsi19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
index 3d810473ec..3eda77db5a 100644
--- a/arch/mips/dts/brcm,bcm63268.dtsi
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -63,6 +63,25 @@
mask = <0x1>;
};
+ gpio1: gpio-controller@100000c0 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <20>;
+
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller@100000c4 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x100000c4 0x4>, <0x100000cc 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
uart0: serial@10000180 {
compatible = "brcm,bcm6345-uart";
reg = <0x10000180 0x18>;