Merge git://git.denx.de/u-boot-x86

20 files changed, 135 insertions, 91 deletions

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5c8dc822ef..c26710b484 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -542,6 +542,19 @@ config VGA_BIOS_ADDR
 	  address of 0xfff90000 indicates that the image will be put at offset
 	  0x90000 from the beginning of a 1MB flash device.
 
+config ROM_TABLE_ADDR
+	hex
+	default 0xf0000
+	help
+	  All x86 tables happen to like the address range from 0x0f0000
+	  to 0x100000. We use 0xf0000 as the starting address to store
+	  those tables, including PIRQ routing table, Multi-Processor
+	  table and ACPI table.
+
+config ROM_TABLE_SIZE
+	hex
+	default 0x10000
+
 menu "System tables"
 	depends on !EFI && !SYS_COREBOOT
 
diff --git a/arch/x86/config.mk b/arch/x86/config.mk
index 74b87ceac5..8835dcf36f 100644
--- a/arch/x86/config.mk
+++ b/arch/x86/config.mk
@@ -10,8 +10,7 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
 PLATFORM_CPPFLAGS += -fno-strict-aliasing
 PLATFORM_CPPFLAGS += -fomit-frame-pointer
 PF_CPPFLAGS_X86   := $(call cc-option, -fno-toplevel-reorder, \
-		       $(call cc-option, -fno-unit-at-a-time)) \
-		     $(call cc-option, -mpreferred-stack-boundary=2)
+		     $(call cc-option, -fno-unit-at-a-time))
 
 PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
 PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
@@ -27,7 +26,7 @@ endif
 ifeq ($(IS_32BIT),y)
 PLATFORM_CPPFLAGS += -march=i386 -m32
 else
-PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common
+PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -m64
 endif
 
 PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig
index 4e7d4a4e25..9374c121f9 100644
--- a/arch/x86/cpu/baytrail/Kconfig
+++ b/arch/x86/cpu/baytrail/Kconfig
@@ -7,7 +7,24 @@
 config INTEL_BAYTRAIL
 	bool
 	select HAVE_FSP if !EFI
+	select ARCH_MISC_INIT if !EFI
+	imply HAVE_INTEL_ME if !EFI
+	imply ENABLE_MRC_CACHE
 	imply ENV_IS_IN_SPI_FLASH
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply SCSI
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply USB_XHCI_HCD
+	imply VIDEO_VESA
 
 if INTEL_BAYTRAIL
 config INTERNAL_UART
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index 87ba849c1c..c58f6a86a8 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -11,18 +11,6 @@
 #include <asm/mrccache.h>
 #include <asm/post.h>
 
-static struct pci_device_id mmc_supported[] = {
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2 },
-	{},
-};
-
-int cpu_mmc_init(bd_t *bis)
-{
-	return pci_mmc_init("ValleyView SDHCI", mmc_supported);
-}
-
 #ifndef CONFIG_EFI_APP
 int arch_cpu_init(void)
 {
diff --git a/arch/x86/cpu/broadwell/Kconfig b/arch/x86/cpu/broadwell/Kconfig
index 1ce3848be3..b421f18202 100644
--- a/arch/x86/cpu/broadwell/Kconfig
+++ b/arch/x86/cpu/broadwell/Kconfig
@@ -6,6 +6,18 @@
 config INTEL_BROADWELL
 	bool
 	select CACHE_MRC_BIN
+	select ARCH_EARLY_INIT_R
+	imply HAVE_INTEL_ME
+	imply ENABLE_MRC_CACHE
+	imply ENV_IS_IN_SPI_FLASH
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_BROADWELL_GPIO
+	imply SCSI
+	imply SPI_FLASH
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_BROADWELL_IGD
 
 if INTEL_BROADWELL
 
diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c
index 436c6c49c3..4fa4de3525 100644
--- a/arch/x86/cpu/broadwell/refcode.c
+++ b/arch/x86/cpu/broadwell/refcode.c
@@ -56,7 +56,17 @@ struct rmodule_header {
 	uint32_t padding[4];
 } __packed;
 
-int cpu_run_reference_code(void)
+/**
+ * cpu_run_reference_code() - Run the platform reference code
+ *
+ * Some platforms require a binary blob to be executed once SDRAM is
+ * available. This is used to set up various platform features, such as the
+ * platform controller hub (PCH). This function should be implemented by the
+ * CPU-specific code.
+ *
+ * @return 0 on success, -ve on failure
+ */
+static int cpu_run_reference_code(void)
 {
 	struct pei_data _pei_data __aligned(8);
 	struct pei_data *pei_data = &_pei_data;
@@ -111,3 +121,8 @@ int cpu_run_reference_code(void)
 
 	return 0;
 }
+
+int arch_early_init_r(void)
+{
+	return cpu_run_reference_code();
+}
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 9820651931..d4e0587fc5 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -3,6 +3,20 @@ if TARGET_COREBOOT
 config SYS_COREBOOT
 	bool
 	default y
+	imply ENV_IS_NOWHERE
+	imply AHCI_PCI
+	imply E1000
+	imply ICH_SPI
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply USB_XHCI_HCD
+	imply VIDEO_COREBOOT
 	imply CMD_CBFS
 	imply FS_CBFS
 
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 658b900f0b..df5ad13821 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -29,11 +29,6 @@ int arch_cpu_init(void)
 	return x86_cpu_init_f();
 }
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int checkcpu(void)
 {
 	return 0;
@@ -90,8 +85,3 @@ int misc_init_r(void)
 {
 	return 0;
 }
-
-int arch_misc_init(void)
-{
-	return 0;
-}
diff --git a/arch/x86/cpu/efi/efi.c b/arch/x86/cpu/efi/efi.c
index 741613f615..d82147be47 100644
--- a/arch/x86/cpu/efi/efi.c
+++ b/arch/x86/cpu/efi/efi.c
@@ -13,11 +13,6 @@ int arch_cpu_init(void)
 	return 0;
 }
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int checkcpu(void)
 {
 	return 0;
@@ -36,8 +31,3 @@ int misc_init_r(void)
 {
 	return 0;
 }
-
-int arch_misc_init(void)
-{
-	return 0;
-}
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index e23d01a08f..00f99d6b11 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -8,6 +8,17 @@
 config NORTHBRIDGE_INTEL_IVYBRIDGE
 	bool
 	select CACHE_MRC_BIN if HAVE_MRC
+	imply HAVE_INTEL_ME
+	imply ENABLE_MRC_CACHE
+	imply ENV_IS_IN_SPI_FLASH
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply SCSI
+	imply SPI_FLASH
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_VESA
 
 if NORTHBRIDGE_INTEL_IVYBRIDGE
 
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 643d804e35..1cdbe479fd 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -233,7 +233,6 @@ static int sdram_find(struct udevice *dev)
 	uint32_t tseg_base, uma_size, tolud;
 	uint64_t tom, me_base, touud;
 	uint64_t uma_memory_base = 0;
-	uint64_t uma_memory_size;
 	unsigned long long tomk;
 	uint16_t ggc;
 	u32 val;
@@ -298,7 +297,6 @@ static int sdram_find(struct udevice *dev)
 		tolud += uma_size << 10;
 		/* UMA starts at old TOLUD */
 		uma_memory_base = tomk * 1024ULL;
-		uma_memory_size = uma_size * 1024ULL;
 		debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
 	}
 
@@ -312,13 +310,11 @@ static int sdram_find(struct udevice *dev)
 		debug("%uM UMA", uma_size >> 10);
 		tomk -= uma_size;
 		uma_memory_base = tomk * 1024ULL;
-		uma_memory_size += uma_size * 1024ULL;
 
 		/* GTT Graphics Stolen Memory Size (GGMS) */
 		uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
 		tomk -= uma_size;
 		uma_memory_base = tomk * 1024ULL;
-		uma_memory_size += uma_size * 1024ULL;
 		debug(" and %uM GTT\n", uma_size >> 10);
 	}
 
@@ -327,7 +323,6 @@ static int sdram_find(struct udevice *dev)
 	uma_size = (uma_memory_base - tseg_base) >> 10;
 	tomk -= uma_size;
 	uma_memory_base = tomk * 1024ULL;
-	uma_memory_size += uma_size * 1024ULL;
 	debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
 
 	debug("Available memory below 4GB: %lluM\n", tomk >> 10);
diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig
index 6808c9a6b9..fdf5ae338e 100644
--- a/arch/x86/cpu/qemu/Kconfig
+++ b/arch/x86/cpu/qemu/Kconfig
@@ -6,6 +6,14 @@
 
 config QEMU
 	bool
+	select ARCH_EARLY_INIT_R
+	imply ENV_IS_NOWHERE
+	imply AHCI_PCI
+	imply E1000
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_VESA
 
 if QEMU
 
diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig
index 163caac660..7ec46e95ef 100644
--- a/arch/x86/cpu/quark/Kconfig
+++ b/arch/x86/cpu/quark/Kconfig
@@ -7,6 +7,21 @@
 config INTEL_QUARK
 	bool
 	select HAVE_RMU
+	select ARCH_EARLY_INIT_R
+	select ARCH_MISC_INIT
+	imply ENABLE_MRC_CACHE
+	imply ENV_IS_IN_SPI_FLASH
+	imply ETH_DESIGNWARE
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
 
 if INTEL_QUARK
 
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 0c2cea4ee9..c36a5892d5 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -16,11 +16,6 @@
 #include <asm/arch/msg_port.h>
 #include <asm/arch/quark.h>
 
-static struct pci_device_id mmc_supported[] = {
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
-	{},
-};
-
 static void quark_setup_mtrr(void)
 {
 	u32 base, mask;
@@ -328,11 +323,6 @@ int arch_early_init_r(void)
 	return 0;
 }
 
-int cpu_mmc_init(bd_t *bis)
-{
-	return pci_mmc_init("Quark SDHCI", mmc_supported);
-}
-
 int arch_misc_init(void)
 {
 #ifdef CONFIG_ENABLE_MRC_CACHE
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 6136d75422..d1b04c952a 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -8,6 +8,22 @@ config INTEL_QUEENSBAY
 	bool
 	select HAVE_FSP
 	select HAVE_CMC
+	select ARCH_EARLY_INIT_R
+	imply ENV_IS_IN_SPI_FLASH
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply PCH_GBE
+	imply SCSI
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_VESA
 
 if INTEL_QUEENSBAY
 
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index af3ffad385..c0681995bd 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -5,4 +5,4 @@
 #
 
 obj-y += fsp_configs.o irq.o
-obj-y += tnc.o topcliff.o
+obj-y += tnc.o
diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c
deleted file mode 100644
index b76dd7de69..0000000000
--- a/arch/x86/cpu/queensbay/topcliff.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <pci_ids.h>
-
-static struct pci_device_id mmc_supported[] = {
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
-	{},
-};
-
-int cpu_mmc_init(bd_t *bis)
-{
-	return pci_mmc_init("Topcliff SDHCI", mmc_supported);
-}
diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig
index b67c6a799e..86a334047c 100644
--- a/arch/x86/cpu/tangier/Kconfig
+++ b/arch/x86/cpu/tangier/Kconfig
@@ -7,6 +7,14 @@
 config INTEL_TANGIER
 	bool
 	depends on INTEL_MID
+	imply INTEL_MID_SERIAL
+	imply MMC
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply MMC_SDHCI_TANGIER
+	imply TANGIER_WATCHDOG
+	imply USB
+	imply USB_DWC3
 
 config SYS_CAR_ADDR
 	hex
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index c00687a20a..bc2c4ffd9f 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -288,16 +288,4 @@ u32 cpu_get_family_model(void);
  */
 u32 cpu_get_stepping(void);
 
-/**
- * cpu_run_reference_code() - Run the platform reference code
- *
- * Some platforms require a binary blob to be executed once SDRAM is
- * available. This is used to set up various platform features, such as the
- * platform controller hub (PCH). This function should be implemented by the
- * CPU-specific code.
- *
- * @return 0 on success, -ve on failure
- */
-int cpu_run_reference_code(void);
-
 #endif
diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h
index 9e8208ba2b..c784a2aeec 100644
--- a/arch/x86/include/asm/tables.h
+++ b/arch/x86/include/asm/tables.h
@@ -9,13 +9,8 @@
 
 #include <tables_csum.h>
 
-/*
- * All x86 tables happen to like the address range from 0xf0000 to 0x100000.
- * We use 0xf0000 as the starting address to store those tables, including
- * PIRQ routing table, Multi-Processor table and ACPI table.
- */
-#define ROM_TABLE_ADDR	0xf0000
-#define ROM_TABLE_END	0xfffff
+#define ROM_TABLE_ADDR	CONFIG_ROM_TABLE_ADDR
+#define ROM_TABLE_END	(CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1)
 
 #define ROM_TABLE_ALIGN	1024