diff options
| author | Wenyou Yang <wenyou.yang@atmel.com> | 2016-07-20 17:16:25 +0800 |
|---|---|---|
| committer | Andreas Bießmann <andreas@biessmann.org> | 2016-08-15 22:58:03 +0200 |
| commit | 46ed9381b7be1ede9783970be3d3141007653c2b (patch) | |
| tree | b61e1d18090fdbe7a77c8f24e0427045848ecc02 /arch/arm/mach-at91 | |
| parent | d51e9a1d04ab77ee26da534172c0c3891dc8ac4f (diff) | |
gpio: atmel_pio4: Move PIO4 definitions to head file
In order to make these PIO4 definitions shared with AT91 PIO4
pinctrl driver, move them from the existing gpio driver to the
head file, and rephrase them.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/mach-at91')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/atmel_pio4.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h index 8bb4b12b26..6760bec452 100644 --- a/arch/arm/mach-at91/include/mach/atmel_pio4.h +++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h @@ -29,6 +29,41 @@ struct atmel_pio4_port { #endif +/* + * PIO Configuration Register Fields + */ +#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) +#define ATMEL_PIO_CFGR_FUNC_GPIO (0x0 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_A (0x1 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_B (0x2 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_C (0x3 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_D (0x4 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_E (0x5 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_F (0x6 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_G (0x7 << 0) +#define ATMEL_PIO_DIR_MASK BIT(8) +#define ATMEL_PIO_PUEN_MASK BIT(9) +#define ATMEL_PIO_PDEN_MASK BIT(10) +#define ATMEL_PIO_IFEN_MASK BIT(12) +#define ATMEL_PIO_IFSCEN_MASK BIT(13) +#define ATMEL_PIO_OPD_MASK BIT(14) +#define ATMEL_PIO_SCHMITT_MASK BIT(15) +#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) +#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) + +#define ATMEL_PIO_NPINS_PER_BANK 32 +#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) +#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) +#define ATMEL_PIO_BANK_OFFSET 0x40 + +#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) +#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) +#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) + #define AT91_PIO_PORTA 0x0 #define AT91_PIO_PORTB 0x1 #define AT91_PIO_PORTC 0x2 |