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authormaxims@google.com <maxims@google.com>2017-04-17 12:00:32 -0700
committerTom Rini <trini@konsulko.com>2017-05-08 11:57:35 -0400
commit3b95902d47f89f95242ac143cd2a9ed1fd196157 (patch)
tree7018c0a0ad6c2d1c042734274addbb39fb648f42 /arch/arm/dts/ast2500-u-boot.dtsi
parent7a88543b50db930a19929fd87d04a1ff48ec35f5 (diff)
aspeed: Add support for Clocks needed by MACs
Add support for clocks needed by MACs to ast2500 clock driver. The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and PCLK_MAC2 for MAC1 and MAC2 respectively. The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed SDK. It is not entirely clear from the datasheet how this clock is used by MACs, so not clear if the rate would ever need to be different. So, for now, hardcoding it is probably safer. The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through hardware strapping. So, the network driver would only need to enable these clocks, no need to configure the rate. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/dts/ast2500-u-boot.dtsi')
-rw-r--r--arch/arm/dts/ast2500-u-boot.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index faeeec1be4..f826646095 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -61,3 +61,11 @@
};
};
};
+
+&mac0 {
+ clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+};
+
+&mac1 {
+ clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
+};