px30.c additions - needs cleanup

1 files changed, 26 insertions, 27 deletions

diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
index 87a7284d78..e4e25b8a60 100644
--- a/arch/arm/mach-rockchip/px30/px30.c
+++ b/arch/arm/mach-rockchip/px30/px30.c
@@ -16,7 +16,6 @@
 #include <dt-bindings/clock/px30-cru.h>
 
 #define PMU_PWRDN_CON			0xff000018
-#define GRF_CPU_CON1			0xff140504
 
 #define VIDEO_PHY_BASE			0xff2e0000
 
@@ -51,8 +50,16 @@ static struct mm_region px30_mem_map[] = {
 struct mm_region *mem_map = px30_mem_map;
 #endif
 
+#define GRF_BASE		0xff140000
+#define CRU_BASE		0xff2b0000
+
+
+#define GRF_CPU_CON1			0xff140504
+
 int arch_cpu_init(void)
 {
+	static struct px30_grf * const grf = (void *)GRF_BASE;
+printf("%s: basic px30 setup\n", __func__);
 #ifdef CONFIG_SPL_BUILD
 	/* We do some SoC one time setting here. */
 	/* Disable the ddr secure region setting to make it non-secure */
@@ -72,26 +79,34 @@ int arch_cpu_init(void)
 	/* Clear the force_jtag */
 	rk_clrreg(GRF_CPU_CON1, 1 << 7);
 
+/* does not seem to help */
+	/* emmc pinmux */
+	rk_clrsetreg(GRF_BASE + 0x8, 0xfff0, 0x2220);
+	rk_clrsetreg(GRF_BASE + 0x0, 0xffff, 0x2222);
+	rk_clrsetreg(GRF_BASE + 0x4, 0xffff, 0x2222);
+
+	/* emmc pull + drv */
+	rk_clrsetreg(GRF_BASE + 0x60, 0xffff, 0x5555);
+	rk_clrsetreg(GRF_BASE + 0x64, 0x3c, 0x10);
+	rk_clrsetreg(GRF_BASE + 0xf0, 0xffff, 0xaaaa);
+	rk_clrsetreg(GRF_BASE + 0xf4, 0x3c, 0x28);
+
+#if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || CONFIG_DEBUG_UART_BASE != 0xff160000
+	/* fix sdmmc pinmux if not used as debug uart */
+	rk_clrsetreg(GRF_BASE + 0x18, 0xff00, 0x1100);
+	rk_clrsetreg(GRF_BASE + 0x1c, 0xffff, 0x1111);
+#endif
+
 	return 0;
 }
 
-
 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 void board_debug_uart_init(void)
 {
-#define GRF_BASE		0xff140000
-#define UART1_BASE		0xff158000
-#define UART2_BASE		0xff160000
-#define UART5_BASE		0xff1
-
-#define CRU_BASE		0xff2b0000
 	static struct px30_grf * const grf = (void *)GRF_BASE;
-
 	static struct px30_cru * const cru = (void *)CRU_BASE;
 
 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)
-//	static struct rk_uart * const uart = (void *)UART1_BASE;
-
 	/* GRF_GPIO1CL_IOMUX */
 	enum {
 		GPIO1C1_SHIFT		= 4,
@@ -117,12 +132,7 @@ void board_debug_uart_init(void)
 		     GPIO1C1_MASK | GPIO1C0_MASK,
 		     GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
 		     GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
-
-	/* enable FIFO */
-//	writel(0x1, &uart->sfe);
-
 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
-
 	/* GRF_GPIO3AL_IOMUX */
 	enum {
 		GPIO3A2_SHIFT		= 8,
@@ -148,12 +158,7 @@ void board_debug_uart_init(void)
 		     GPIO3A2_MASK | GPIO3A1_MASK,
 		     GPIO3A2_UART5_TX << GPIO3A2_SHIFT |
 		     GPIO3A1_UART5_RX << GPIO3A1_SHIFT);
-
-
-
 #else
-	static struct rk_uart * const uart = (void *)UART2_BASE;
-
 	/* GRF_GPIO1DL_IOMUX */
 	enum {
 		GPIO1D3_SHIFT		= 12,
@@ -195,9 +200,6 @@ void board_debug_uart_init(void)
 
 //#ifdef CONFIG_TPL_BUILD
 
-	/* Clear the force_jtag */
-	rk_clrreg(GRF_CPU_CON1, 1 << 7);
-
 	/* uart_sel_clk default select 24MHz */
 	rk_clrsetreg(&cru->clksel_con[37],
 		     UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK,
@@ -222,9 +224,6 @@ void board_debug_uart_init(void)
 	rk_clrsetreg(&grf->gpio2bh_iomux,
 		     GPIO2B4_MASK,
 		     GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT);
-
-	/* enable FIFO */
-	writel(0x1, &uart->sfe);
 //#else
 //#ifdef CONFIG_SPL_BUILD