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authorChristoffer Dall <christoffer.dall@linaro.org>2016-05-25 15:26:33 +0100
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-06-24 10:22:01 -0700
commit05be09606e9421fe2b4af0f37a5420216efd0ecc (patch)
treec99f54ba0274f8986bb008ecba12cdd1b2632f9c /virt
parent48fc8f94672afcaf5900f3e40761a25c6912c39c (diff)
KVM: arm/arm64: vgic-v2: Clear all dirty LRs
commit 4d3afc9bad2b67b118a0cc204dc94703f7a44e74 upstream. When saving the state of the list registers, it is critical to reset them zero, as we could otherwise leave unexpected EOI interrupts pending for virtual level interrupts. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'virt')
-rw-r--r--virt/kvm/arm/hyp/vgic-v2-sr.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/virt/kvm/arm/hyp/vgic-v2-sr.c b/virt/kvm/arm/hyp/vgic-v2-sr.c
index 674bdf8ecf4f..501849ad0b60 100644
--- a/virt/kvm/arm/hyp/vgic-v2-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v2-sr.c
@@ -93,12 +93,11 @@ static void __hyp_text save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
continue;
- if (cpu_if->vgic_elrsr & (1UL << i)) {
+ if (cpu_if->vgic_elrsr & (1UL << i))
cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
- continue;
- }
+ else
+ cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
- cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
writel_relaxed(0, base + GICH_LR0 + (i * 4));
}
}