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authorH. Nikolaus Schaller <hns@goldelico.com>2016-08-02 14:07:12 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2016-08-02 19:35:40 -0400
commitecfaf0c42fc4306b5ec4bf6be01b66f8fe9a9733 (patch)
tree0f7789f2c47a3d52db2e5a59d39d6f794e0e9fd5 /init
parent939fc832290d548a02b6a309992b3c1ff7de1ff9 (diff)
w1:omap_hdq: fix regression
Commit e93762bbf681 ("w1: masters: omap_hdq: add support for 1-wire mode") added a statement to clear the hdq_irqstatus flags in hdq_read_byte(). If the hdq reading process is scheduled slowly or interrupts are disabled for a while the hardware read activity might already be finished on entry of hdq_read_byte(). And hdq_isr() already has set the hdq_irqstatus to 0x6 (can be seen in debug mode) denoting that both, the TXCOMPLETE and RXCOMPLETE interrupts occurred in parallel. This means there is no need to wait and the hdq_read_byte() can just read the byte from the hdq controller. By resetting hdq_irqstatus to 0 the read process is forced to be always waiting again (because the if statement always succeeds) but the hardware will not issue another RXCOMPLETE interrupt. This results in a false timeout. After such a situation the hdq bus hangs. Link: http://lkml.kernel.org/r/b724765f87ad276a69625bc19806c8c8844c4590.1469513669.git.hns@goldelico.com Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Cc: Evgeniy Polyakov <zbr@ioremap.net> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: <stable@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'init')
0 files changed, 0 insertions, 0 deletions