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authorAlexey Brodkin <abrodkin@synopsys.com>2015-12-07 14:21:37 +0300
committerVineet Gupta <vgupta@synopsys.com>2015-12-07 19:40:03 +0530
commit6d1a2adef782d26113d4f18a617ccb33c4774d54 (patch)
tree2500cafdee89d0e1ada0d397262b7b19b4f1ffb0 /arch/arc
parent31ade3b83e1821da5fbb2f11b5b3d4ab2ec39db8 (diff)
ARC: [axs10x] cap ethernet phy to 100 Mbit/sec
Current ARC SDP boards cannot reliably handle 1Gbit Ethernet connections due to limitations in hardware. To make sure networking is stable on the board we're limiting phy to 100 Mbit. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc')
-rw-r--r--arch/arc/boot/dts/axs10x_mb.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index f3db32154973..44a578c10732 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -46,6 +46,7 @@
snps,pbl = < 32 >;
clocks = <&apbclk>;
clock-names = "stmmaceth";
+ max-speed = <100>;
};
ehci@0x40000 {