diff options
| author | Finley Xiao <finley.xiao@rock-chips.com> | 2019-01-18 15:40:18 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2019-01-23 18:39:16 +0800 |
| commit | 85115a5899052ec3dbe6f91a91eb45aeb8552886 (patch) | |
| tree | f22042cb5e8224bb3f548203e9a0af795e33d389 | |
| parent | 65848fcd2563f813feb758dd33177c0f84cfdef8 (diff) | |
PM / devfreq: rockchip_dmc: Implement rk3399_set_msch_readlatency()
The ATF must contain the following commit:
cd61876e275e ("plat: rk3399: ddr: add support adjust noc read latency")
Change-Id: I322f8c9d454fb1234b042438c85521275ceda4bc
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
| -rw-r--r-- | drivers/devfreq/rockchip_dmc.c | 14 | ||||
| -rw-r--r-- | include/soc/rockchip/rockchip_sip.h | 1 |
2 files changed, 15 insertions, 0 deletions
diff --git a/drivers/devfreq/rockchip_dmc.c b/drivers/devfreq/rockchip_dmc.c index df114ebd8f38..5bc54f15350f 100644 --- a/drivers/devfreq/rockchip_dmc.c +++ b/drivers/devfreq/rockchip_dmc.c @@ -1166,6 +1166,7 @@ struct rockchip_dmcfreq { u64 touchboostpulse_endtime; int (*set_auto_self_refresh)(u32 en); + int (*set_msch_readlatency)(unsigned int rl); }; static struct thermal_opp_device_data dmc_devdata = { @@ -2533,6 +2534,17 @@ static __maybe_unused int rk3368_dmc_init(struct platform_device *pdev, return 0; } +static int rk3399_set_msch_readlatency(unsigned int readlatency) +{ + struct arm_smccc_res res; + + arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, readlatency, 0, + ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL, + 0, 0, 0, 0, &res); + + return res.a0; +} + static __maybe_unused int rk3399_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq) { @@ -2568,6 +2580,8 @@ static __maybe_unused int rk3399_dmc_init(struct platform_device *pdev, ROCKCHIP_SIP_CONFIG_DRAM_INIT, 0, 0, 0, 0, &res); + dmcfreq->set_msch_readlatency = rk3399_set_msch_readlatency; + return 0; } diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h index bca3ffb31655..630f9b85899c 100644 --- a/include/soc/rockchip/rockchip_sip.h +++ b/include/soc/rockchip/rockchip_sip.h @@ -25,5 +25,6 @@ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 #define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08 #define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE 0x09 +#define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL 0x0a #endif |