diff options
author | Sandy Huang <hjc@rock-chips.com> | 2019-01-18 14:56:14 +0800 |
---|---|---|
committer | Tao Huang <huangtao@rock-chips.com> | 2019-01-21 09:11:18 +0800 |
commit | 5778016ed8e997ce2181cf205d00719e0b99a4d7 (patch) | |
tree | dedfbdfe7caa483fd5446f96c79ca2993df6f5c0 | |
parent | 172be0a14153b8b2c28f0f548e3e9839a81ee5c5 (diff) |
phy/rockchip: mipi-dphy: leave move margin for clk post time
Change-Id: I64dc251fb7e0efea1e1cf8d7ce05f792187a5c4d
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
-rw-r--r-- | drivers/phy/rockchip/phy-rockchip-inno-mipi-dphy.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-mipi-dphy.c b/drivers/phy/rockchip/phy-rockchip-inno-mipi-dphy.c index d70aba4905ba..b2ee0020ecf4 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-mipi-dphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-mipi-dphy.c @@ -371,7 +371,11 @@ static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, { /* Global Operation Timing Parameters */ timing->clkmiss = 0; - timing->clkpost = 70 + 52 * period / PSEC_PER_NSEC; + /* + * The D-PHY spec define the clk post min time is 60ns + 52UI and + * no define max time, so we set 200 + 52UI leave move margin. + */ + timing->clkpost = 200 + 52 * period / PSEC_PER_NSEC; timing->clkpre = 8 * period / PSEC_PER_NSEC; timing->clkprepare = 65; timing->clksettle = 95; |