phy: rockchip: mipi-dphy-rx: support for rk3368

Change-Id: I51cc5c4015bb3567bb19c08f0fb4ea422b13e937
Signed-off-by: Cai YiWei <cyw@rock-chips.com>

1 files changed, 84 insertions, 0 deletions

diff --git a/drivers/phy/rockchip/phy-rockchip-mipi-rx.c b/drivers/phy/rockchip/phy-rockchip-mipi-rx.c
index 328507214e7a..000423fba452 100644
--- a/drivers/phy/rockchip/phy-rockchip-mipi-rx.c
+++ b/drivers/phy/rockchip/phy-rockchip-mipi-rx.c
@@ -61,6 +61,9 @@
 #define RK3326_GRF_IO_VSEL_OFFSET	0x0180
 #define RK3326_GRF_PD_VI_CON_OFFSET	0x0430
 
+#define RK3368_GRF_SOC_CON6_OFFSET	0x0418
+#define RK3368_GRF_IO_VSEL_OFFSET	0x0900
+
 #define RK3399_GRF_SOC_CON9	0x6224
 #define RK3399_GRF_SOC_CON21	0x6254
 #define RK3399_GRF_SOC_CON22	0x6258
@@ -99,6 +102,10 @@
 #define RK3326_CSI_DPHY_CTRL_PWRCTL		0x04
 #define RK3326_CSI_DPHY_CTRL_DIG_RST		0x80
 
+#define RK3368_CSI_DPHY_CTRL_LANE_ENABLE	0x00
+#define RK3368_CSI_DPHY_CTRL_PWRCTL		0x04
+#define RK3368_CSI_DPHY_CTRL_DIG_RST		0x80
+
 #define MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT	2
 #define MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT	6
 
@@ -123,6 +130,16 @@
 #define RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE	\
 		(RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
 
+#define RK3368_CSI_DPHY_CLK_WR_THS_SETTLE	0x100
+#define RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE	\
+		(RK3368_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
+#define RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE	\
+		(RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
+#define RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE	\
+		(RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
+#define RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE	\
+		(RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
+
 /* Calibration reception enable */
 #define RK1808_CSI_DPHY_CLK_CALIB_EN		0x168
 #define RK1808_CSI_DPHY_LANE0_CALIB_EN		0x1e8
@@ -141,6 +158,16 @@
 #define RK3326_CSI_DPHY_LANE3_CALIB_EN		\
 		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
 
+#define RK3368_CSI_DPHY_CLK_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3368_CSI_DPHY_LANE0_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3368_CSI_DPHY_LANE1_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3368_CSI_DPHY_LANE2_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3368_CSI_DPHY_LANE3_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
 /*
  * CSI HOST
  */
@@ -192,6 +219,8 @@ enum dphy_reg_id {
 	GRF_DPHY_CSIPHY_FORCERXMODE,
 	GRF_DPHY_CSIPHY_CLKLANE_EN,
 	GRF_DPHY_CSIPHY_DATALANE_EN,
+	/* rk3368 only */
+	GRF_ISP_MIPI_CSI_HOST_SEL,
 	/* below is for rk3399 only */
 	GRF_DPHY_RX0_CLK_INV_SEL,
 	GRF_DPHY_RX1_CLK_INV_SEL,
@@ -300,6 +329,13 @@ static const struct dphy_reg rk3326_grf_dphy_regs[] = {
 	[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
 };
 
+static const struct dphy_reg rk3368_grf_dphy_regs[] = {
+	[GRF_DVP_V18SEL] = PHY_REG(RK3368_GRF_IO_VSEL_OFFSET, 1, 1),
+	[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
+	[GRF_ISP_MIPI_CSI_HOST_SEL] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 1),
+	[GRF_CON_DISABLE_ISP] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 0),
+};
+
 static const struct dphy_reg rk3399_grf_dphy_regs[] = {
 	[GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
 	[GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
@@ -375,6 +411,22 @@ static const struct csiphy_reg rk3326_csiphy_regs[] = {
 	[CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_CALIB_EN),
 };
 
+static const struct csiphy_reg rk3368_csiphy_regs[] = {
+	[CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_LANE_ENABLE),
+	[CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_PWRCTL),
+	[CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_DIG_RST),
+	[CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_CLK_WR_THS_SETTLE),
+	[CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE),
+	[CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE),
+	[CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE),
+	[CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE),
+	[CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_CLK_CALIB_EN),
+	[CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE0_CALIB_EN),
+	[CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE1_CALIB_EN),
+	[CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE2_CALIB_EN),
+	[CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE3_CALIB_EN),
+};
+
 struct hsfreq_range {
 	u32 range_h;
 	u8 cfg_bit;
@@ -753,6 +805,13 @@ static const struct hsfreq_range rk3326_mipidphy_hsfreq_ranges[] = {
 	{1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
 };
 
+static const struct hsfreq_range rk3368_mipidphy_hsfreq_ranges[] = {
+	{ 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
+	{ 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
+	{ 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
+	{1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
+};
+
 static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = {
 	{  89, 0x00}, {  99, 0x10}, { 109, 0x20}, { 129, 0x01},
 	{ 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
@@ -779,6 +838,10 @@ static const char * const rk3326_mipidphy_clks[] = {
 	"dphy-ref",
 };
 
+static const char * const rk3368_mipidphy_clks[] = {
+	"pclk_dphyrx",
+};
+
 static const char * const rk3399_mipidphy_clks[] = {
 	"dphy-ref",
 	"dphy-cfg",
@@ -790,6 +853,12 @@ static void default_mipidphy_individual_init(struct mipidphy_priv *priv)
 {
 }
 
+static void rk3368_mipidphy_individual_init(struct mipidphy_priv *priv)
+{
+	/* isp select */
+	write_grf_reg(priv, GRF_ISP_MIPI_CSI_HOST_SEL, 1);
+}
+
 static void rk3399_mipidphy_individual_init(struct mipidphy_priv *priv)
 {
 	/*
@@ -1100,6 +1169,17 @@ static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
 	.individual_init = default_mipidphy_individual_init,
 };
 
+static const struct dphy_drv_data rk3368_mipidphy_drv_data = {
+	.clks = rk3368_mipidphy_clks,
+	.num_clks = ARRAY_SIZE(rk3368_mipidphy_clks),
+	.hsfreq_ranges = rk3368_mipidphy_hsfreq_ranges,
+	.num_hsfreq_ranges = ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges),
+	.grf_regs = rk3368_grf_dphy_regs,
+	.csiphy_regs = rk3368_csiphy_regs,
+	.ctl_type = MIPI_DPHY_CTL_CSI_HOST,
+	.individual_init = rk3368_mipidphy_individual_init,
+};
+
 static const struct dphy_drv_data rk3399_mipidphy_drv_data = {
 	.clks = rk3399_mipidphy_clks,
 	.num_clks = ARRAY_SIZE(rk3399_mipidphy_clks),
@@ -1125,6 +1205,10 @@ static const struct of_device_id rockchip_mipidphy_match_id[] = {
 		.data = &rk3326_mipidphy_drv_data,
 	},
 	{
+		.compatible = "rockchip,rk3368-mipi-dphy",
+		.data = &rk3368_mipidphy_drv_data,
+	},
+	{
 		.compatible = "rockchip,rk3399-mipi-dphy",
 		.data = &rk3399_mipidphy_drv_data,
 	},