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authorPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2015-01-06 21:26:44 +0100
committerKlaus Goger <klaus.goger@theobroma-systems.com>2015-07-30 18:44:04 +0200
commitb2b385df5095fff80b4655142f58a2a6801e6c80 (patch)
treee16d8372076ed67d51c2d93eadfdf0031feb45ac /snapshot.commit
parent098e4100da724481e9cf117ec87aa29fd7680feb (diff)
sun6i: Fix and document PLL LDO voltage selection
The PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had their meaning reversed. This is fixed by this change-set. With this changed, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident as setting the voltage to 1.37v (which it had done all along, even though stating a different target voltage). After changing the PLL LDO setting, it will take a little while for the voltage output to settle. A sdelay()-based loop waits the same order of magnitude as Boot1. Furthermore, a bit of documentation is added to clarify that the required setting for the PLL LDO is 1.37v as per the A31 manual.
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