sun6i: Fix and document PLL LDO voltage selection

The PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had
their meaning reversed. This is fixed by this change-set. With this
changed, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident
as setting the voltage to 1.37v (which it had done all along, even
though stating a different target voltage).

After changing the PLL LDO setting, it will take a little while for
the voltage output to settle. A sdelay()-based loop waits the same
order of magnitude as Boot1.

Furthermore, a bit of documentation is added to clarify that the
required setting for the PLL LDO is 1.37v as per the A31 manual.

1 files changed, 15 insertions, 2 deletions

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index fa7ebd8060..3a6e56e300 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -24,14 +24,27 @@ void clock_init_safe(void)
 	struct sunxi_prcm_reg * const prcm =
 		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
-	/* Set PLL ldo voltage without this PLL6 does not work properly */
+	/* Set PLL ldo voltage without this PLL6 does not work properly.
+	 *
+	 * As the A31 manual states, that "before enable PLL, PLLVDD
+	 * LDO should be set to 1.37v", we need to configure this to 2.5v
+	 * in the "PLL Input Power Select" (0 << 15) and (7 << 16).
+	 */
 	clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
 			PRCM_PLL_CTRL_LDO_KEY);
 	clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
 		PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
-		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
+		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370) );
 	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
 
+	/* Give the PLL LDO voltage setting some time to take hold.
+	 * Notes:
+	 *   1) We need to use sdelay() as the timers aren't set up yet.
+	 *   2) The 100k iterations come from Boot1, which spin's for 100k
+	 *      iterations through a loop.
+	 */
+	sdelay(100000);
+
 	clock_set_pll1(408000000);
 
 	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);