arm: armada-xp: Add SPL support used to include the DDR training code

This patch adds SPL support to the Marvell Armada-XP. With this addition
the bin_hdr integration is not needed any more. The SPL will first
initialize the serdes/PHY and the call the DDR setup and training code
now integrated into mainline U-Boot.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>

1 files changed, 62 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
new file mode 100644
index 0000000000..1febd7bac5
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
@@ -0,0 +1,62 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+	bx	lr
+ENDPROC(save_boot_params)
+
+/*
+ * cache_inv - invalidate Cache line
+ * r0 - dest
+ */
+	.global cache_inv
+	.type  cache_inv, %function
+	cache_inv:
+
+	stmfd   sp!, {r1-r12}
+
+	mcr     p15, 0, r0, c7, c6, 1
+
+	ldmfd   sp!, {r1-r12}
+	bx      lr
+
+
+/*
+ * flush_l1_v6 - l1 cache clean invalidate
+ * r0 - dest
+ */
+	.global flush_l1_v6
+	.type	flush_l1_v6, %function
+	flush_l1_v6:
+
+	stmfd   sp!, {r1-r12}
+
+	mcr     p15, 0, r0, c7, c10, 5	/* @ data memory barrier */
+	mcr     p15, 0, r0, c7, c14, 1	/* @ clean & invalidate D line */
+	mcr     p15, 0, r0, c7, c10, 4	/* @ data sync barrier */
+
+	ldmfd   sp!, {r1-r12}
+	bx      lr
+
+
+/*
+ * flush_l1_v7 - l1 cache clean invalidate
+ * r0 - dest
+ */
+	.global flush_l1_v7
+	.type	flush_l1_v7, %function
+	flush_l1_v7:
+
+	stmfd   sp!, {r1-r12}
+
+	dmb				/* @data memory barrier */
+	mcr     p15, 0, r0, c7, c14, 1	/* @ clean & invalidate D line */
+	dsb				/* @data sync barrier */
+
+	ldmfd   sp!, {r1-r12}
+	bx      lr