diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6q.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6q.dtsi | 76 |
1 files changed, 30 insertions, 46 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 93ec79bb6b35..cd10c8de1904 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -14,6 +14,7 @@ / { aliases { + ipu1 = &ipu2; spi4 = &ecspi5; }; @@ -21,7 +22,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; @@ -103,42 +104,6 @@ iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6q-iomuxc"; - - ipu2 { - pinctrl_ipu2_1: ipu2grp-1 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10 - MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000 - MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10 - >; - }; - }; }; }; @@ -153,6 +118,16 @@ status = "disabled"; }; + gpu_vg: gpu@02204000 { + compatible = "vivante,gc"; + reg = <0x02204000 0x4000>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_GPU2D_CORE>; + clock-names = "bus", "core"; + power-domains = <&gpc 1>; + }; + ipu2: ipu@02800000 { #address-cells = <1>; #size-cells = <0>; @@ -187,6 +162,7 @@ }; ipu2_di0_mipi: endpoint@2 { + remote-endpoint = <&mipi_mux_2>; }; ipu2_di0_lvds0: endpoint@3 { @@ -208,6 +184,7 @@ }; ipu2_di1_mipi: endpoint@2 { + remote-endpoint = <&mipi_mux_3>; }; ipu2_di1_lvds0: endpoint@3 { @@ -225,6 +202,11 @@ compatible = "fsl,imx-display-subsystem"; ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; }; + + gpu-subsystem { + compatible = "fsl,imx-gpu-subsystem"; + cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>; + }; }; &hdmi { @@ -294,19 +276,21 @@ }; &mipi_dsi { - port@2 { - reg = <2>; + ports { + port@2 { + reg = <2>; - mipi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_mipi>; + mipi_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_mipi>; + }; }; - }; - port@3 { - reg = <3>; + port@3 { + reg = <3>; - mipi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_mipi>; + mipi_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_mipi>; + }; }; }; }; |