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authorChen-Yu Tsai <wens@csie.org>2015-08-11 13:32:57 +0800
committerHerbert Xu <herbert@gondor.apana.org.au>2015-08-13 15:13:27 +0800
commit14fee74ca8370e4bfa5c9386e63bfa521b37a505 (patch)
tree137ee6b257eb84fe372029c39bb01d835a9c8350 /arch
parent7ab64628bb4ab139aea9f1238ce6f945be580773 (diff)
ARM: dts: sun6i: Add security system crypto engine clock and device nodes
A31/A31s have the same "Security System" crypto engine as A10/A20, but with a separate reset control. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 008047a018cf..e79c14d3db2b 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -346,6 +346,14 @@
"mmc3_sample";
};
+ ss_clk: clk@01c2009c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2009c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "ss";
+ };
+
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -870,6 +878,16 @@
#size-cells = <0>;
};
+ crypto: crypto-engine@01c15000 {
+ compatible = "allwinner,sun4i-a10-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 5>, <&ss_clk>;
+ clock-names = "ahb", "mod";
+ resets = <&ahb1_rst 5>;
+ reset-names = "ahb";
+ };
+
timer@01c60000 {
compatible = "allwinner,sun6i-a31-hstimer",
"allwinner,sun7i-a20-hstimer";