diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-10-02 13:42:21 +0900 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2015-10-27 09:21:02 +0900 |
| commit | 7c62f299bafef82c83169ac0c4cf77874446fc83 (patch) | |
| tree | ff7f1ce4d392a456c0394e9946ae1befca0aaf8f /arch/arm/boot/dts/uniphier-ph1-pro4.dtsi | |
| parent | 3d2ef3b3962c60e3b25de6a981127d95cb0be98b (diff) | |
ARM: dts: uniphier: add outer cache controller nodes
Add L2 cache controller nodes for all the UniPhier SoC DTSI.
Also, add an L3 cache controller node for PH1-Pro5 DTSI.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/uniphier-ph1-pro4.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/uniphier-ph1-pro4.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi index e8bbc454d788..85377b23483f 100644 --- a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi @@ -56,12 +56,14 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + next-level-cache = <&l2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + next-level-cache = <&l2>; }; }; @@ -98,6 +100,18 @@ #size-cells = <1>; }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(768 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; |