diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2013-12-05 16:14:09 +0530 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-12-16 14:09:20 -0700 |
| commit | a47c662aad72cbabdb0e8df6c25c47c68b400e40 (patch) | |
| tree | 08f552fd4229686cf54db0a06eb1d911c7aec563 /arch/arm/boot/dts/tegra30-cardhu.dtsi | |
| parent | ba4104e79470ae848a9f38029fe1371790dc0df9 (diff) | |
ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl defines
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra30 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-cardhu.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra30-cardhu.dtsi | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 748b4ba945ee..f3aab9eb6453 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -59,8 +59,8 @@ sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc1_cmd_pz1 { nvidia,pins = "sdmmc1_cmd_pz1", @@ -69,14 +69,14 @@ "sdmmc1_dat2_py5", "sdmmc1_dat3_py4"; nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc3_cmd_pa7 { nvidia,pins = "sdmmc3_cmd_pa7", @@ -85,15 +85,15 @@ "sdmmc3_dat2_pb5", "sdmmc3_dat3_pb4"; nvidia,function = "sdmmc3"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc4_clk_pcc4 { nvidia,pins = "sdmmc4_clk_pcc4", "sdmmc4_rst_n_pcc3"; nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdmmc4_dat0_paa0 { nvidia,pins = "sdmmc4_dat0_paa0", @@ -105,8 +105,8 @@ "sdmmc4_dat6_paa6", "sdmmc4_dat7_paa7"; nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; dap2_fs_pa2 { nvidia,pins = "dap2_fs_pa2", @@ -114,17 +114,17 @@ "dap2_din_pa4", "dap2_dout_pa5"; nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; sdio3 { nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <0>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; nvidia,pull-down-strength = <46>; nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = <1>; - nvidia,slew-rate-falling = <1>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; }; uart3_txd_pw6 { nvidia,pins = "uart3_txd_pw6", @@ -132,8 +132,8 @@ "uart3_rts_n_pc0", "uart3_rxd_pw7"; nvidia,function = "uartc"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; }; }; }; |