diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-02-28 17:40:22 +0100 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2014-02-28 10:23:44 -0700 |
| commit | ad6be7d1146daa90be90e924fd5fb07a22d8ffda (patch) | |
| tree | bca761ecfd143ba6519d76ab9315ec92e75e0fe9 /arch/arm/boot/dts/tegra124.dtsi | |
| parent | 4989b439237dabe80e842b2e2c3743b847b87c2d (diff) | |
ARM: tegra: Add Tegra124 host1x support
The version of host1x on Tegra124 is largely compatible with that on
earlier Tegra generations. Some of the registers have moved around or
expanded to allow for more capability, so a separate compatible string
is still required.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 30a7377d5600..26dfe09e8410 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -9,6 +9,47 @@ compatible = "nvidia,tegra124"; interrupt-parent = <&gic>; + host1x@50000000 { + compatible = "nvidia,tegra124-host1x", "simple-bus"; + reg = <0x50000000 0x00034000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ + clocks = <&tegra_car TEGRA124_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x01000000>; + + dc@54200000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_DISP1>, + <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + nvidia,head = <0>; + }; + + dc@54240000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_DISP2>, + <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + nvidia,head = <1>; + }; + }; + gic: interrupt-controller@50041000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; |