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authorHeiko Stuebner <heiko@sntech.de>2014-09-10 16:28:02 +0200
committerHeiko Stuebner <heiko@sntech.de>2014-09-13 20:28:13 +0200
commit39c2bd782a2c50c51bced96ad3f2c97d4997d949 (patch)
tree35b08466012771a3c34375f1d06d3ef79337853a /arch/arm/boot/dts/rk3xxx.dtsi
parentf1c8547f56f1da9db51fe3281479c823e949a9fd (diff)
ARM: dts: rockchip: add Cortex-A9 SPI controller nodes
This adds basic spi nodes and pinctrl settings to the rk3066 and rk3188 devicetree files. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3xxx.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3xxx.dtsi24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index c873624af6aa..7bcd69855052 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -26,6 +26,8 @@
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
+ spi0 = &spi0;
+ spi1 = &spi1;
};
xin24m: oscillator {
@@ -291,4 +293,26 @@
clock-names = "saradc", "apb_pclk";
status = "disabled";
};
+
+ spi0: spi@20070000 {
+ compatible = "rockchip,rk3066-spi";
+ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x20070000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@20074000 {
+ compatible = "rockchip,rk3066-spi";
+ clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x20074000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};