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authorShawn Guo <shawn.guo@linaro.org>2012-08-11 12:49:11 +0800
committerShawn Guo <shawn.guo@linaro.org>2012-09-11 16:26:47 +0800
commit9e3c00665d915c4f5645d43aec5a943b5eee55de (patch)
tree548bb515941368f912a212a73862c4b8a9747d93 /arch/arm/boot/dts/imx6q.dtsi
parent99d5f0cc17c0c7191e1bb9dc40849a1711a77439 (diff)
ARM: dts: imx6q-arm2: add pinctrl for uart and enet
Add missing pinctrl of uart and enet for imx6q-arm2 board. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 9d180220212a..f6c99f722f4c 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -552,6 +552,26 @@
48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
>;
};
+
+ pinctrl_enet_2: enetgrp-2 {
+ fsl,pins = <
+ 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
+ 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
+ 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+ 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+ 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+ 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+ 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+ 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+ 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+ 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+ 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+ 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+ 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+ 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+ 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+ >;
+ };
};
gpmi-nand {
@@ -598,6 +618,15 @@
};
};
+ uart4 {
+ pinctrl_uart4_1: uart4grp-1 {
+ fsl,pins = <
+ 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
+ 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
+ >;
+ };
+ };
+
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <