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authorHaojian Zhuang <haojian.zhuang@linaro.org>2014-05-07 08:55:29 +0800
committerWei Xu <xuwei5@hisilicon.com>2014-09-03 14:10:37 +0100
commit40c7d4414b44a75971ba7c1a4fc1371dd7a299bf (patch)
treee4991eff46e5a1f5da32da10fbdb1fd5b8e28e4f /arch/arm/boot/dts/hip04-d01.dts
parentf2b22ab5b32bbc801a3e205d60667ebb546ee39c (diff)
ARM: dts: add hip04 dts
Add hip04-d01.dts & hip04.dtsi for hip04 SoC platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm/boot/dts/hip04-d01.dts')
-rw-r--r--arch/arm/boot/dts/hip04-d01.dts32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts
new file mode 100644
index 000000000000..40a9e33c2654
--- /dev/null
+++ b/arch/arm/boot/dts/hip04-d01.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2013-2014 Linaro Ltd.
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "hip04.dtsi"
+
+/ {
+ /* memory bus is 64-bit */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Hisilicon D01 Development Board";
+ compatible = "hisilicon,hip04-d01";
+
+ memory@00000000,10000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000 0x00000000 0xc0000000>,
+ <0x00000004 0xc0000000 0x00000003 0x40000000>;
+ };
+
+ soc {
+ uart0: uart@4007000 {
+ status = "ok";
+ };
+ };
+};