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authorRoman Byshko <rbyshko@gmail.com>2014-02-07 16:21:50 +0100
committerEmilio López <emilio@elopez.com.ar>2014-02-18 09:35:20 -0300
commit5abdbf2f497c1769aa9df284ad125d40641207c7 (patch)
tree509821c3ef31d80f99c825e39086ab036cc7bf2f /Documentation/devicetree/bindings/clock/sunxi.txt
parentcfb0086dca781ac7ab9b63e6c8088064c29a4118 (diff)
clk: sunxi: Add USB clock register defintions
Add register definitions for the usb-clk register found on sun4i, sun5i and sun7i SoCs. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/sunxi.txt')
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt5
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 0cf679b8384f..ca2b6920fca4 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -37,6 +37,8 @@ Required properties:
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
"allwinner,sun7i-a20-out-clk" - for the external output clocks
+ "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
+ "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
Required properties for all clocks:
- reg : shall be the control register address for the clock.
@@ -50,6 +52,9 @@ Required properties for all clocks:
If the clock module only has one output, the name shall be the
module name.
+And "allwinner,*-usb-clk" clocks also require:
+- reset-cells : shall be set to 1
+
Clock consumers should specify the desired clocks they use with a
"clocks" phandle cell. Consumers that are using a gated clock should
provide an additional ID in their clock property. This ID is the