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authorStefan Agner <stefan@agner.ch>2016-02-10 16:02:25 -0800
committerShawn Guo <shawnguo@kernel.org>2016-02-29 16:17:33 +0800
commit6af2f61a293d3032dc5f59bea314355d6b7743e2 (patch)
treef6ab12c5d1dd867da00efd6c472f6ac38d36c640
parentddcc6cad715319fff53968db7110a287dbc4a77e (diff)
ARM: dts: vf610twr: assign Ethernet clock explicitly
Assign Ethernet clock parents explicitly. The VF610 Tower Board uses the external Ethernet clock input which is connected to a 50MHz clock. The Vybrid SoC has two ethernet interfaces (fec0 and fec1) which use the same clock source (VF610_CLK_ENET). Therefore this parent configuration affects multiple consumer devices and need to be specified in the clock provider node. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index ce937b9fcf00..cdc100732514 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -128,6 +128,10 @@
&clks {
clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
+ assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
+ <&clks VF610_CLK_ENET_TS_SEL>;
+ assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>,
+ <&clks VF610_CLK_ENET_EXT>;
};
&dspi0 {